FAN6754 Fairchild Semiconductor, FAN6754 Datasheet - Page 11

• Manufacturer Part Number: FAN6754
• Description: The highly integrated FAN6754 PWM controller provides several features to enhance the performance of flyback converters
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN6754 • Rev. 1.0.2
Functional Description
Startup Current
For startup, the HV pin is connected to the line input
through an external diode and resistor; R
150KΩ recommended). Peak startup current drawn
from the HV pin is (V
hold-up capacitor through the diode and resistor. When
the V
current switches off. At this moment, the V
only supplies the FAN6754 to keep the V
auxiliary winding of the main transformer provides the
operating current.
Operating Current
Operating current is around 1.7mA. The low operating
current enables better efficiency and reduces the
requirement of V
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in light-
load and no-load conditions. V
the voltage feedback loop, is taken as the reference.
Once V
switching frequency is continuously decreased to the
minimum green-mode frequency of around 22KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current-sense signal and V
When the voltage on the SENSE pin reaches around
V
immediately. V
voltage around 0.46V for low-line output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 9V, respectively. During startup, the hold-
up capacitor must be charged to 16.5V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply V
delivered from auxiliary winding of the main transformer.
V
hysteresis window ensures that hold-up capacitor is
adequate to supply V
COMP
DD
must not drop below 9V during startup. This UVLO
DD
= (V
FB
capacitor level reaches V
is lower than the threshold voltage (V
FB
–0.6)/4, the switch cycle is terminated
COMP
DD
hold-up capacitance.
is internally clamped to a variable
DD
AC
during startup.
DD
×
until the energy can be
2
FB
) / R
FB
, the feedback voltage.
, which is derived from
HV
DD-ON
and charges the
HV
, the startup
DD
, (1N4007 /
DD
capacitor
until the
FB-N
),
11
V
V
AC
AC
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
13V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and cycle-by-cycle
current limiting. Built-in slope compensation improves
stability
FAN6754 inserts a synchronized, positive-going, ramp
at every switching cycle.
Constant Output Power Limit
When the SENSE voltage across sense resistor R
reaches the threshold voltage, around 0.46V for low-line
condition, the output GATE drive is turned off after a
small delay, t
current proportional to t
nearly constant regardless of the input voltage V
higher input voltage results in a larger additional current
and the output power limit is higher than under low input
line voltage. To compensate this variation for a wide AC
input range, a power-limiter is controlled by the HV pin
to solve the unequal power-limit problem. The power
limiter is fed to the inverting input of the current limiting
comparator. This results in a lower current limit at high-
line inputs than at low-line inputs.
Brownout and Constant Power Limited by
HV Pin
Unlike previous PWM controllers, FAN6754’s HV pin
can detect the AC line voltage brownout function and
adjust the current limit level. Using a fast diode and
startup resistor to sample the AC line voltage, the peak
value refreshes and is stored in a register at each
sampling cycle. When internal update time is met, this
peak value is used for brownout and current-limit level
judgment. Equation 1 and 2 calculate the level of
brownin or brownout converted to RMS value. For
power saving, FAN6754 enlarges the sampling cycle to
lower the power loss from HV sampling at light load
condition.
-
-
ON
OFF
(RMS)
(RMS)
=
=
and
(
(
0.9V
0.81V
PD
×
. This delay introduces an additional
×
prevents
(R
(R
HV
1.6
HV
1.6
+
1.6)
+
PD
1.6)
/ )
• V
/ )
sub-harmonic
2
IN
2
/ L
;
the
P
. Since the delay is
unit
of
R
www.fairchildsemi.com
HV
oscillation.
is
k
Ω
SENSE
IN
(1)
(2)
,