74LCX16543MTDX Fairchild Semiconductor, 74LCX16543MTDX Datasheet
74LCX16543MTDX
Specifications of 74LCX16543MTDX
Related parts for 74LCX16543MTDX
74LCX16543MTDX Summary of contents
Page 1
... Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2001 Fairchild Semiconductor Corporation Features 5V tolerant inputs and outputs 2.3V–3.6V V ...
Page 2
Pin Descriptions Pin Names OEAB n OEBA n CEAB n CEBA n LEAB n LEBA n A – – Data I/O Control Table Inputs CEAB LEAB HIGH Voltage ...
Page 3
Logic Diagrams Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. Byte 1 (0:7) Byte 2 (8:15) 3 www.fairchildsemi.com ...
Page 4
Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Source/Sink Current Supply ...
Page 5
DC Electrical Characteristics Symbol Parameter I Quiescent Supply Current CC I Increase in I per Input CC CC Note 5: Outputs in disabled or 3-STATE only. AC Electrical Characteristics Symbol Parameter t Propagation Delay PHL ...
Page 6
AC LOADING and WAVEFORMS FIGURE 1. AC Test Circuit (C Waveform for Inverting and Non-Inverting Functions Propagation Delay. Pulse Width and t rec 3-STATE Output Low Enable and Disable Times for Logic (Input Characteristics; f =1MHz, t Symbol V mi ...
Page 7
Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com ...
Page 8
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide www.fairchildsemi.com Package Number MS56A 8 ...
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...