FIN3385 Fairchild Semiconductor, FIN3385 Datasheet - Page 8

• Manufacturer Part Number: FIN3385
• Description: Fin3385 * Fin3383 * Fin3384 * Fin3386 Low Voltage 28-bit Flat Panel Display Link Serializers/deserializers
• Manufacturer: Fairchild Semiconductor

www.fairchildsemi.com
LVTTL/CMOS DC Characteristics
V
V
V
V
V
I
I
I
Receiver LVDS Input Characteristics
V
V
V
I
Receiver Supply Current
I
I
I
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Receiver DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 16)
Note 16: All Typical values are at T
current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except
Note 17: The power supply current for the receiver can be different with the number of active I/O channels.
Note 18: Total channel latency from Sewrializer to deserializer is (T
Note 19: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position.
IN
OFF
OS
IN
CCWR
CCWR
CCPDT
RCOP
RCOL
RCOH
RSRC
RHRC
ROLH
ROHL
RCCD
RPDD
RSPB0
RSPB1
RSPB2
RSPB3
RSPB4
RSPB5
RSPB6
RSKM
RPLLS
Symbol
IH
IL
OH
OL
IK
TH
TL
ICM
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Clamp Voltage
Input Current
Input/Output Power Off Leakage Current
Output Short Circuit Current
Differential Input Threshold HIGH
Differential Input Threshold LOW
Input Common Mode Range
Input Current
4:28 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 17)
3:21 Receiver Power Supply Current
for Worst Case Pattern (With Load)
(Note 17)
Powered Down Supply Current
Receiver Clock Output (RxCLKOut) Period
RxCLKOut LOW Time
RxCLKOut HIGH Time
RxOut Valid Prior to RxCLKOut
RxOut Valid After RxCLKOut
Output Rise Time (20% to 80%)
Output Fall Time (80% to 20%)
Receiver Clock Input to Clock Output Delay
Receiver Power-Down Delay
Receiver Input Strobe Position of Bit 0
Receiver Input Strobe Position of Bit 1
Receiver Input Strobe Position of Bit 2
Receiver Input Strobe Position of Bit 3
Receiver Input Strobe Position of Bit 4
Receiver Input Strobe Position of Bit 5
Receiver Input Strobe Position of Bit 6
RxIN Skew Margin
Receiver Phase Lock Loop Set Time
Parameter
A
25
q
C and with V
CC
3.3V. Positive current values refer to the current flowing into device and negative values means

t
TCCD
I
I
I
V
V
All LVTTL Inputs/Outputs 0V to 4.6V
V
Figure 2, Table 2
Figure 2, Table 2
Figure 2, Table 2
V
V
C
See Figure 3
C
See Figure 3
PwrDn
See Figure 8
(f
(Rising Edge Strobe)
C
See Figure 4
See Figure 20, (Note 18)
T
See Figure 13
See Figure 17 (f
See Figure 17, (Note 19)
See Figure 11
OH
OL
IK
IN
CC
OUT
IN
IN
A
L
L
L
). There is the clock period.
85MHz)

8 pF,
8 pF,
8 pF,
25
8
2mA

0V to 4.6V
2.4V, V
0V, V
18 mA
0V,
0.4 mA
q
0V
C and V
0.8V (RxOut stays LOW)
Test Conditions
CC
CC
3.6V or 0V
CC
3.6V or 0V
85MHz)
'
3.3V
V
OD
32.5 MHz
40.0 MHz
66.0 MHz
85.0 MHz
32.5 MHz
40.0 MHz
66.0 MHz
85.0 MHz
and V
OD
).

10.57
11.76
GND

0.05
0.49
2.17
3.85
5.53
7.21
8.89
Min
290
2.0
2.7
10.0
4.0
4.5
3.5
3.5
3.5
100


10.92
0.06
49.0
53.0
78.0
90.0
0.84
2.52
4.20
5.88
7.56
9.24
Typ
3.3
0.79
60.0
NA
5.0
5.0
2.0
1.8
5.0
T
r
r
r
11.27

Max
V

10.0
2.35
70.0
75.0
60.0
65.0
55.0
50.0
1.19
2.87
4.55
6.23
7.91
9.59
10.0
100
135
100
114
115
0.8
0.3
10.0
10.0
10.0
6.0
6.5
3.5
3.5
7.5
1.0
120
1.5
CC
Units
mA
mV
mV
mA
mA
P
P
P
P
P
ms
ns
ns
ns
ns
ns
ns
ns
P
ns
ns
ns
ns
ns
ns
ns
ps
V
V
V
V
V
V
A
A
A
A
A
s