FIN1108 Fairchild Semiconductor, FIN1108 Datasheet - Page 5

• Manufacturer Part Number: FIN1108
• Description: Fin1108 * Fin1108t Preliminary Lvds 8 Port High Speed Repeater
• Manufacturer: Fairchild Semiconductor

t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
PLHD
PHLD
TLHD
THLD
SK(P)
SK(LH)
SK(HL)
SK(PP)
MAX
PZHD
PZLD
PHZD
PLZD
DJ
RJ
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Note 3: All typical values are at T
Note 4: t
tion.
Note 5: t
(either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6: Passing criteria for maximum frequency is the output V
Note 7: Output loading is transmission line environment only; C
Symbol
FIGURE 1. Differential Receiver Voltage Definitions
,
FIGURE 2. Differential Driver DC Test Circuit
SK(LH)
SK(PP)
Differential Output Propagation Delay
LOW-to-HIGH
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Rise Time (20% to 80%) V
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
Differential Output Disable Time
from LOW to Z
LVDS Data Jitter,
Deterministic
LVDS Clock Jitter,
Random (RMS)
, t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
PLH
Parameter
- t
A
PHL
25 C and with V
|
CC
3.3V.
R
V
Duty Cycle
See Figure 1 and Figure 1
R
See Figure 2 and Figure 3
V
V
V
V
L
ID
IC
L
ID
IC
ID
IC
OD
L
is
100 , C
100 , C
200 mV to 450 mV,
V
300 mV, PRBS
1.2V at 800 Mbps
300 mV,
1.2V at 400 MHz
250 mV and the duty cycle is better than 45% / 55% with all channels switching.
ID
1 pF of stray test fixture capacitance.
/2 to V
Test Conditions
50%,
L
L
CC
5
5 pF,
5 pF,
Note A: All LVDS input pulses have frequency
Note B: C
(V
FIGURE 3. Differential Driver Propagation Delay
ID
2
or t
23
/2),
L
- 1,
F
includes all probe and jig capacitances
0.5 ns
and Transition Time Test Circuit
0.29
0.75
0.75
0.29
Min
400
(Note 3)
0.02
0.02
0.02
Typ
1.1
1.1
0.4
0.4
3.1
2.2
2.5
1.9
630
80
3
10 MHz, t
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Max
1.75
1.75
0.58
0.58
0.15
R
135
0.2
0.5
3.5
5
5
5
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps