FIN12AC Fairchild Semiconductor, FIN12AC Datasheet
FIN12AC
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FIN12AC Summary of contents
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... Fairchild Semiconductor Corporation. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 Description The FIN12AC is a 12-bit serializer / deserializer capable of running a parallel frequency range between 5MHz and 40MHz, selected by the S1 and S2 control signals. The bi-directional data flow is controlled through use of a direction (DIRI) control pin. The devices can be config- ...
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... Functional Block Diagram CKREF STROBE DP[21:22] DP[1:20] DP[23:24] CKP S1 S2 DIRI © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 PLL 0 I cksint Serializer Control Serializer oe Deserializer Deserializer cksint Control WORD CK Generator Control Logic DIRO Freq Direction Control Control oe Power Down Control Figure 1. Block Diagram 2 + CKS0+ ...
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... The DSO/DSI serial port pins have been arranged such that if one device is rotated 180° with respect to the other 1 device, the serial connections properly aligns without the need for any traces or cable signals to cross. Other layout orientations may require that traces or cables cross © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 Number of Terminals 12 LVCMOS parallel I/O, Direction controlled by DIRI pin ...
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... DP[7] 6 DP[8] 7 DP[9] 8 (Top View) BGA Pin Assignments 1 A DP4 B DP6 C CKP D N/C E DP8 F DP10 G DP12 N Connect © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 CKSO+ 24 CKSO- 23 DSO+/DSI- 22 DSO-/DSI+ 21 CKSI- 20 CKSI+ 19 DIRI DDS Figure 2. Terminal and Pin Assignments DP2 N/C N/C ...
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... Control Logic Circuitry The FIN12AC can be used as a 12-bit serializer or a 12- bit deserializer. Terminals S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 shows the terminal program- ming of these options based on the S1 and S2 control terminals. When DIRI is asserted LOW, the device is configured as a deserializer ...
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... CKREF frequency. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 Serializer Operation: DIRI = 1, No CKREF A third method of serialization uses a free-running bit clock on the CKSI signal. This is enabled by grounding the CKREF signal and driving the DIRI signal HIGH ...
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... The device receives parallel data on the rising edge of STROBE_M. 4. The device generates and transmits serialized data on the DS signals, which is source synchronous with CKSO. 5. The device generates an embedded word clock for each strobe signal. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 From Deserializer To Serializer . DDP BIT CK ...
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... Camera MASTER_CLK Interface PIXEL_CLK YUV[7:0] HSYNC VSYNC Note: V does not have to equal V DD1 Figure 6. Unidirectional 8-bit YUV Sensor with Master Clock on Base (10MHz to 40MHz Operation) © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 V 2.775 DD1 DDP DDA DDS DDS FIN12AC ...
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... STROBE Pass-Through Mode For some applications desirable to pass a word clock across a differential signal pair in the opposite direction of serialization. The FIN12AC supports this mode of operation. For the deserializer: 1. DIRI = LOW 2. CKREF = LOW 3. Word clock should be connected to the STROBE. This passes the STROBE signal out the CKSO port. ...
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... Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Supply Voltage DDA DDS V Supply Voltage DDP T Operating Temperature A V Supply Noise Voltage DDA-PP © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 Parameter Parameter 10 Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V Continuous -65 +150 °C +150 ° ...
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... R TRM Termination Resistor CKSI Internal Receiver R TRM Termination Resistor Note : the difference in device ground levels between the CTL driver and the CTL receiver. GO © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 Test Conditions V = 3.3 ±0.30 DDP I = –2.0mA V = 2.5 ±0.20 OH DDP V = 1.8 ±0.15 DDP V = 3.3 ± ...
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... DDA 14:1 Dynamic Deserializer I Power Supply Current DD_DES1 DD_DES1 DDA © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 values. Typical values are measured Test Conditions All DP and Control Inputs NOCKREF DIR = 1 All DP and Control Inputs NOCKREF ...
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... Data Valid to CKP LOW PDV t Output Rise Time (20% to 80%) ROLH t Output Fall Time (80% to 20%) ROHL © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 = 2.775V and T = 25°C. Positive current values refer to the current flowing into A ). Test Conditions CKREF = STROBE Figure 13 CKREF does not = ...
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... STROBE, S1, S2, DIRI C Capacitance of Parallel Port Pins DP[1:12 Capacitance of Differential I/O Signals IO-DIFF © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 Test Conditions DIRI LOW-to-HIGH or HIGH-to-LOW DIRI LOW-to-HIGH DIRI HIGH-to-LOW DIRI = 0, S1( and S2(1) = LOW-to-HIGH Figure 21 DIRI = 0, S1( and S2(1) = LOW-to-HIGH ...
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... DD t TLH 80% V 20% DIFF V = (DS+) – (DS-) DIFF DS – DS- Figure 10. CTL Output Load and Transition Times © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 DS+ DUT DS- T 999h values. Minimum values are measured at the minimum V DD Figure 9. “Worst Case” Serializer Test Pattern ...
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... CKREF 25 RCOH Setup: DIRI = “0”, CKSI and DS are valid signals. Figure 14. Deserializer Data Valid Window Time and Clock Output Parameters © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 (Continued) Data t HTC t PDV 50% RCOL Note: CKREF Signa is free running. ...
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... Figure 18. PLL Loss of Clock Disable Time t PLZ(HZ DS+,CKS0+ HIGHZ DS–,CKS0- Note: CKREF must be active and PLL must be stable. Figure 20. Serializer Enable and Disable Time © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 (Continued) CKSO- CKSO+ t H_DS DSO+ DSO- Figure 17. Differential Output Signal Skew CKS0 Figure 19 ...
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... Sketch A (Side or Front Sectional View) Component Rotation Dia A max Tape Dia A Dim B Width Max. Min. 8 330.0 1.5 12 330.0 1.5 16 330.0 1.5 © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1 Min. ±0.1 ±0.1 ±0.1 Typ ...
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... CONTROL VALUE) 1.00 MAX 0. SEATING PLANE Figure 22. 42-Ball, Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide Note: Click here for tape and reel specifications, available at: http://www.fairchildsemi.com/products/analog/packaging/bga42.html. © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 3.50 2X 0.10 C (0.6) 4.50 0.5 0.89±0.082 0.45±0.05 0.21±0.04 0.23± ...
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... Physical Dimensions (Continued) Figure 23. 32-Terminal, Molded Leadless Package (MLP), Quad, JEDEC MO-220, 5mm Square © 2006 Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 20 www.fairchildsemi.com ...
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... Fairchild Semiconductor Corporation FIN12AC Rev. 1.1.1 21 www.fairchildsemi.com ...