FAN5250 Fairchild Semiconductor, FAN5250 Datasheet - Page 9

• Manufacturer Part Number: FAN5250
• Description: Mobile Processor Core-Voltage Regulator
• Manufacturer: Fairchild Semiconductor

Operation Mode Control
The mode-control circuit changes the converter’s mode of
operation based on the voltage polarity of the SW node when
the lower MOSFET is conducting and just before the upper
MOSFET turns on. For continuous inductor current, the SW
node is negative when the lower MOSFET is conducting and
the converters operate in fixed-frequency PWM mode as
shown in Figure 5. This mode of operation achieves high
efficiency at nominal load. When the load current decreases
to the point where the inductor current flows through the
lower MOSFET in the ‘reverse’ direction, the SW node
becomes positive, and the mode is changed to hysteretic,
which achieves higher efficiency at low currents by decreas-
ing the effective switching frequency.
A comparator handles the timing of the SW node voltage
sensing. A low level on the SW comparator output indicates
a negative SW voltage during the conduction time of the
lower MOSFET. A high level on the comparator output indi-
cates a positive SW voltage. To prevent accidental mode
change and “mode chatter”, the circuit must detect eight con-
secutive matching sign signals in a row before it changes
mode. If during the monitoring process the mismatch of volt-
age signs occurs, no decision to mode change will occur.
This same decision algorithm is used both for changing from
PWM to Hysteretic mode as well as from Hysteretic to
PWM mode.
PWM mode is sustained during all upward and downward
transitions commanded by either VID code change, or during
transitions from ALTV programmed voltage to VID code set
voltage, or vice versa, as well as in Soft-Start.
The boundary value of inductor current, where current
becomes discontinuous, can be estimated by the following
expression.
REV. 1.1.6 3/12/03
V
V
CORE
CORE
I
I
L
L
0
0
I
LOAD DIS
(
)
=
(
------------------------------------------------- -
2 F
V
IN
SW
–
V
L
OUT
1
OUT
Figure 5. Transitioning Between PWM and Hysteresis
)V
V
OUT
PWM Mode
VIN
2
1
2
Hysteretic Mode
3
3
(6)
4
4
Hysteretic Mode
The mode change from hysteretic to PWM can be caused by
one of two events. One event is the same mechanism that
causes a PWM to hysteretic transition. But instead of look-
ing for eight consecutive positive occurrences on the SW
node it is looking for eight consecutive negative occurrences
on the SW node. The operation mode will be changed from
hysteretic to PWM when these eight consecutive pulses
occur. This transition technique prevents jitter of the
operation mode at load levels close to boundary.
The other mechanism for changing from hysteretic to PWM
is due to a sudden increase in the output current. This step
load causes an instantaneous decrease in the output voltage
due to the voltage drop on the output capacitor ESR. If the
decrease causes the output voltage to drop below the hyster-
etic regulation level (20mV below V
to PWM on the next clock cycle. This insures the full power
required by the increase in output current.
In hysteretic mode, the PWM comparator and the error
amplifier that provided control in PWM mode are inhibited
and the hysteretic comparator is activated. In this mode the
synchronous rectifier MOSFET is controlled in diode
emulation mode, where the voltage across it is monitored,
and it is switched off when its voltage goes positive (current
flowing back from the load) allowing the schottky diode to
block reverse conduction.
The hysteretic comparator initiates a PFM signal to turn on
UDRV when the output voltage falls below the lower
threshold (10mV below V
when the output voltage rises over the higher threshold
(5mV above V
5
6
5
7
SS
8
).
6
Hysteretic Mode
SS
) and terminates the PFM signal
7
SS
), the mode is changed
8
PWM Mode
FAN5250
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