74ABT16646CSSC Fairchild Semiconductor, 74ABT16646CSSC Datasheet
74ABT16646CSSC
Specifications of 74ABT16646CSSC
Available stocks
Related parts for 74ABT16646CSSC
74ABT16646CSSC Summary of contents
Page 1
... B register and/or B data may be stored in the A register. Ordering Code: Order Number Package Number 74ABT16646CSSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16646CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “ ...
Page 2
Function Table Inputs OE DIR CPAB CPBA SAB ...
Page 3
Logic Diagram 3 www.fairchildsemi.com ...
Page 4
Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 3) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...
Page 5
DC Electrical Characteristics (SSOP Package) Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V ...
Page 6
Extended AC Electrical Characteristics (SSOP Package) Symbol Parameter t Propagation Delay PLH t Clock to Bus PHL t Propagation Delay PLH t Bus to Bus PHL t Progagation Delay PLH t SBA or SAB PHL n ...
Page 7
Skew (SOIC Package) Symbol Parameter t Pin to Pin Skew OSHL (Note 15) HL Transitions t Pin to Pin Skew OSLH (Note 15) LH Transitions t Duty Cycle PS (Note 16) LH–HL Skew t Pin to Pin Skew OST (Note ...
Page 8
Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...