PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 33

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

4.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a Hi-Impedance Input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
EXAMPLE 4-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are also disabled
on a Power-on Reset.
FIGURE 4-3:
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
2001 Microchip Technology Inc.
Note 1:
RBPU
Data Bus
WR Port
WR TRIS
RD TRIS
RD Port
RB0/INT
2:
PORTB and TRISB Register
STATUS, RP0
STATUS, RP1
PORTB
STATUS, RP0
0xCF
TRISB
(2)
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION<7>).
TRIS Latch
Data Latch
D
D
CK
CK
Schmitt Trigger
Buffer
INITIALIZING PORTB
BLOCK DIAGRAM OF
RB3:RB0 PINS
Q
Q
; Select Bank0
; Initialize PORTB
; Select Bank1
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Q
EN
D
TTL
Input
Buffer
DD
and V
V
RD Port
P
DD
SS
Weak
Pull-up
.
I/O
pin
(1)
Preliminary
Four of the PORTB pins (RB7:RB4) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB7:RB4 pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB7:RB4 are OR’ed together to generate the RB Port
Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt-on-mismatch feature, together with soft-
ware configurable pull-ups on these four pins, allow easy
interface to a keypad and make it possible for wake-up on
key depression. Refer to the Embedded Control Hand-
book, “Implementing Wake-Up on Key Stroke” (AN552).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 4-4:
Set RBIF
Data Bus
WR TRIS
RD TRIS
RD Port
Note 1:
WR Port
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
RBPU
RB7:RB6 in Serial Programming Mode
From other
RB7:RB4 pins
2:
(2)
I/O pins have diode protection to V
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION<7>).
PIC16C925/926
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
BLOCK DIAGRAM OF
RB7:RB4 PINS
Q
Q
Latch
EN
EN
D
D
TTL
Input
Buffer
DS39544A-page 31
DD
V
P
RD Port
DD
and V
Weak
Pull-up
ST
Buffer
I/O
pin
Q1
SS
Q3
(1)
.