PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 64

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

PIC16C925/926
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure
SPI mode, clear bit SSPEN, re-initialize the SSPCON
register, and then set bit SSPEN. This configures the
SDI, SDO, SCK, and SS pins as serial port pins. For the
pins to behave as the serial port function, they must
have their data direction bits (in the TRISC register)
appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value. An example
would be in Master mode, where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
Figure 9-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (CKP), then both con-
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
FIGURE 9-2:
DS39544A-page 62
cleared
be configured such that RA5 is a digital I/O
SPI Master SSPM3:SSPM0 = 00xx b
MSb
SPI MASTER/SLAVE CONNECTION
PROCESSOR 1
Serial Input Buffer
Shift Register
(SSPBUF)
(SSPSR)
LSb
SDO
SCK
SDI
Preliminary
Serial Clock
• Master sends dummy data — Slave sends data
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the firmware protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the interrupt flag bit SSPIF (PIR1<3>)
is set.
The clock polarity is selected by appropriately program-
ming bit CKP (SSPCON<4>). This then, would give
waveforms for SPI communication as shown in
Figure 9-3, Figure 9-4, and Figure 9-5, where the MSB
is transmitted first. In Master mode, the SPI clock rate
(bit rate) is user programmable to be one of the
following:
• F
• F
• F
• Timer2 output/2
This allows a maximum bit clock frequency (at 8 MHz)
of 2 MHz. When in Slave mode, the external clock must
meet the minimum high and low times.
In SLEEP mode, the slave can transmit and receive
data and wake the device from SLEEP.
OSC
OSC
OSC
SDO
SCK
SDI
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
SPI Slave SSPM3:SSPM0 = 010x b
CY
MSb
)
Serial Input Buffer
CY
Shift Register
CY
PROCESSOR 2
(SSPBUF)
)
(SSPSR)
)
2001 Microchip Technology Inc.
LSb