PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 67

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

9.2
This section provides an overview of the Inter-
Integrated Circuit (I
ing the operation of the SSP module in I
The I
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. An enhanced specification, or fast mode is not
supported. This device will communicate with fast
mode devices if attached to the same bus.
The I
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hard-
ware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXXX software. Table 9-2 defines some of the
I
I
ment #939839340011, “The I
which can be obtained from the Philips Corporation.
In the I
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read from/write to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is, they can be thought of as operating in either
of these two relations:
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases, the master generates the clock signal.
TABLE 9-2:
Transmitter
Receiver
Master
Slave
Multi-master
Arbitration
Synchronization
2
2
C bus terminology. For additional information on the
C interface specification, refer to the Philips docu-
2001 Microchip Technology Inc.
2
2
C interface employs a comprehensive protocol to
C bus is a two-wire serial interface developed by
Term
2
C interface protocol, each device has an
I
2
C Overview
I
2
2
C BUS TERMINOLOGY
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock and terminates the transfer.
The device addressed by a master.
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Procedure that ensures that only one of the master devices will control the bus. This ensures that
the transfer data does not get corrupted.
Procedure where the clock signals of two or more devices are synchronized.
C) bus, with Section 9.3 discuss-
2
C bus and how to use it”,
2
C mode.
Preliminary
Description
The output stages of the clock (SCL) and data (SDA)
lines must have an open drain or open collector, in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I
limited only by the maximum bus loading specification
of 400 pF.
9.2.1
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a
high to low transition of the SDA when the SCL is high.
The STOP condition is defined as a low to high transi-
tion of the SDA when the SCL is high. Figure 9-6 shows
the START and STOP conditions. The master gener-
ates these conditions for starting and terminating data
transfer. Due to the definition of the START and STOP
conditions, when data is being transmitted, the SDA
line can only change state when the SCL line is low.
FIGURE 9-6:
SDA
SCL
Condition
START
S
INITIATING AND TERMINATING
DATA TRANSFER
PIC16C925/926
Change
Allowed
of Data
START AND STOP
CONDITIONS
Change
Allowed
of Data
DS39544A-page 65
Condition
STOP
2
P
C bus is