PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 62

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

PIC16C925/926
REGISTER 9-2:
DS39544A-page 60
bit 7
bit 6
bit 5
bit 4
bit 3-0
SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
bit 7
WCOL: Write Collision Detect bit
1 = SSPBUF register is written while still transmitting the previous word (must be cleared in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while SSPBUF is holding previous data. Data in SSPSR is lost on overflow.
0 = No overflow
In I
1 = A byte is received while the SSPBUF is holding the previous byte. SSPOV is a “don’t care” in transmit
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
When enabled, these pins must be properly configured as input or output.
1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I
When enabled, these pins must be properly configured as input or output.
1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin (SS pin control enabled)
0101 = SPI Slave mode, clock = SCK pin (SS pin control disabled, SS can be used as I/O pin)
0110 = I
0111 = I
1011 = I
1110 = I
1111 = I
1000, 1001, 1010, 1100, 1101 = reserved
Legend:
R = Readable bit
- n = Value at POR
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
WCOL
R/W-0
2
2
2
Overflow only occurs in Slave mode. The user must read the SSPBUF, even if only transmitting data,
to avoid setting overflows. In Master mode, the overflow bit is not set since each operation is initiated
by writing to the SSPBUF register. (Must be cleared in software.)
C mode:
mode. (Must be cleared in software.)
C mode:
C mode:
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C firmware controlled Master mode (slave idle)
C firmware controlled Master mode, 7-bit address with START and STOP bit interrupts enabled
C firmware controlled Master mode, 10-bit address with START and STOP bit interrupts enabled
SSPOV
R/W-0
W = Writable bit
’1’ = Bit is set
SSPEN
R/W-0
Preliminary
OSC
OSC
OSC
/4
/16
/64
R/W-0
CKP
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
SSPM3
R/W-0
SSPM2
R/W-0
2001 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
SSPM0
R/W-0
bit 0