PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 71

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

9.3
The SSP module in I
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master func-
tions. The SSP module implements the standard mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC3/SCK/SCL pin, which is the clock (SCL), and the
RC4/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISC<4:3> bits. The SSP module functions are
enabled
(SSPCON<5>).
FIGURE 9-16:
The SSP module has five registers for I
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly
• SSP Address Register (SSPADD)
RC3/SCK/SCL
accessible
2001 Microchip Technology Inc.
RC4/
SDA
SDI/
SSP I
by
setting
Read
2
C Operation
Clock
Shift
MSb
2
C mode fully implements all slave
STOP bit Detect
SSP BLOCK DIAGRAM
(I
Match Detect
SSPADD reg
SSPBUF reg
START and
2
SSPSR reg
SSP
C MODE)
enable
LSb
Write
(SSPSTAT reg)
Data Bus
Set, Reset
2
Addr Match
S, P bits
bit,
Internal
C operation.
SSPEN
Preliminary
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
• I
• I
Selection of any I
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
transfer. The SSPSTAT register is read only.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In
10-bit mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
STOP bit interrupts enabled
STOP bit interrupts enabled
idle
2
2
2
2
2
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Slave mode (7-bit address), with START and
C Slave mode (10-bit address), with START and
C Firmware controlled Master mode, slave is
PIC16C925/926
2
C mode, with the SSPEN bit set,
2
C modes to be selected:
DS39544A-page 69
2
C opera-