PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 85

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

11.0
The LCD module generates the timing control to drive
a static or multiplexed LCD panel, with support for up to
32 segments multiplexed with up to four commons. It
also provides control of the LCD pixel data.
The interface to the module consists of 3 control regis-
ters (LCDCON, LCDSE, and LCDPS), used to define
the timing requirements of the LCD panel and up to 16
LCD data registers (LCD00-LCD15) that represent the
array of the pixel data. In normal operation, the control
registers are configured to match the LCD panel being
used. Primarily, the initialization information consists of
REGISTER 11-1:
2001 Microchip Technology Inc.
LCD MODULE
bit 7
bit 6
bit 5
bit 4
bit 1-0
bit 3-2
LCDCON REGISTER (ADDRESS 10Fh)
LCDEN: Module Drive Enable bit
1 = LCD drive enabled
0 = LCD drive disabled
SLPEN: LCD Display Enabled to SLEEP bit
1 = LCD module will stop driving in SLEEP
0 = LCD module will continue driving in SLEEP
WERR: Write Failed Error bit
1 = System tried to write LCDD register during disallowed time. (Must be reset in software.)
0 = No error
BIAS: Bias Generator Enable bit
0 = Internal bias generator powered down, bias is expected to be provided externally
1 = Internal bias generator enabled, powered up
CS<1:0>: Clock Source bits
00 = F
01 = T1CKI (Timer1)
1x = Internal RC oscillator
LMUX<1:0>: Common Selection bits
Specifies the number of commons
00 = Static(COM0)
01 = 1/2 (COM0, 1)
10 = 1/3 (COM0, 1, 2)
11 = 1/4 (COM0, 1, 2, 3)
bit 7
Legend:
R = Readable bit
- n = Value at POR
LCDEN
R/W-0
OSC
/256
SLPEN
R/W-0
WERR
R/W-0
Preliminary
W = Writable bit
’1’ = Bit is set
R/W-0
BIAS
selecting the number of commons required by the LCD
panel, and then specifying the LCD frame clock rate to
be used by the panel.
Once the module is initialized for the LCD panel, the
individual bits of the LCD data registers are cleared/set
to represent a clear/dark pixel, respectively.
Once
(LCDCON<7>) bit is used to enable or disable the LCD
module. The LCD panel can also operate during
SLEEP by clearing the SLPEN (LCDCON<6>) bit.
Figure 11-2 through Figure 11-5 provides waveforms
for static, half-duty cycle, one-third-duty cycle, and
quarter-duty cycle drives.
the
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
CS1
module
PIC16C925/926
R/W-0
CS0
is
configured,
x = Bit is unknown
LMUX1
R/W-0
DS39544A-page 83
the
LMUX0
R/W-0
LCDEN
bit 0