FAN5355UC07X Fairchild Semiconductor, FAN5355UC07X Datasheet
FAN5355UC07X
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FAN5355UC07X Summary of contents
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... trademark of Philips Corporation. SmartReflex and OMAP are trademarks of Texas Instruments. XSCALE is a trademark of Intel Corporation. NVIDIA is a registered trademark of NVIDIA Corporation. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Description The FAN5355 device is a high-frequency, ultra-fast transient response, optimized for low-power applications using small, low-cost inductors and capacitors ...
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... FAN5355UC02X 02 1 FAN5355UC03X 03 0 (1) FAN5355UC06X 06 0 (1) FAN5355UC07X 07 1 (1) FAN5355MP07X 07 1 Notes: 1. Option 06 and 07 is rated for 1A output current. All other options are rated for 800mA output current limited to the maximum voltage for all VSEL codes greater than the maximum V OUT 3 ...
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... All logic inputs (SDA, SCL, SYNC, EN, and VSEL) are high impedance and should not be left floating. For minimum quiescent power consumption, tie unused logic inputs to AVIN or AGND. If I2C control is unused, tie SDA and SCL to AVIN. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 ...
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... Maximum power dissipation is a function of T allowable ambient temperature is P 11. This thermal data is measured with high-K board (four-layer board according to JESD51-7 JEDEC standard). © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Human Body Model per JESD22-A114 Charged Device Model per JESD22-C101 ( long as the pull-up voltage for SDA and SCL is less than 2 ...
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... Oscillator Frequency SW f Synchronization Range SYNC D Synchronization Duty Cycle SYNC f SYNC Frequency Rejection SYNCVAL f Minimum PFM Frequency PFM(MIN) © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Conditions I = 0mA, EPFM Mode 25kHz O PFM I = 0mA, NPFM Mode 0mA, 3MHz PWM Mode GND ...
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... V OUT Load Regulation Δ I LOAD Δ V OUT Line Regulation Δ Output Ripple Voltage RIPPLE © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 (Continued) Conditions Forced PWM 1.35V OUT(DC) OUT 2.7V ≤ V ≤ 5.5V, V from 0.75 to 1.5375, IN OUT 800mA, Forced PWM OUT(DC) 2.7V ≤ ...
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... Option 06 slew rate is 35.5V/ms during the first 16μs of soft-start. AVIN EN VSEL SYNC INTERFACE AND LOGIC SDA SCL 3 MHz Osc © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Conditions Option 07 All Other Options Monotonicity Assured by Design R = 75Ω, Transition from 1.0 to 1.5375V LOAD V Settled to within 2% of Setpoint OUT R > ...
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... START Condition and After ACK Bit t SDA Fall Time FDA t Stop Condition Setup Time SU;STO C Capacitive Load for SDA and SCL B © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Conditions Standard mode Fast mode High-Speed mode, C < 100pF B High-Speed mode, C < 400pF ...
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... HD;STA REPEATED START = MCS Current Source Pull- Resistor Pull-up P Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. Figure 6. I © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 t SU;STA T SU;DAT t HD;STA REPEATED 2 C Interface Timing for Fast and Slow Modes ...
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... Auto PWM/NPFM 70% Forced PWM 60% 50% 40% 30% 20% 10 Output Current (ma) LOAD Figure 9. Efficiency vs. Load at V © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 = 3.6V 25°C, and recommended components as specified in Table 100% 90% 80% 70% 60% 50% 40% 30% VIN = 3.6 V 20% VOUT = 1.05 V 10% ...
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... Temperature (C) Figure 14 Shift vs. Temperature (Normalized) OUT © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 = 3.6V 25°C, and recommended components as specified in Table 1.364 1.362 1.360 1.358 1.356 1.354 1.352 1.350 1.348 100 ...
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... Typical Performance Characteristics Unless otherwise specified 3.6V Load Transient Response Figure 16. 50mA to 400mA to 50mA, Forced PWM Figure 18. 400mA to 750mA to 400mA, Auto PWM/NPFM © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 (Continued) = 1.35V, and load step < 100ns. OUT R F Figure 17. 50mA to 400mA to 50mA, Auto PWM/NPFM Figure 19 ...
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... Typical Performance Characteristics Unless otherwise specified 3.6V. IN VSEL Transitions Figure 20. Single-Step, R Figure 22. Single-Step, R © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 (Continued) = 6.2Ω LOAD = 50Ω LOAD 13 Figure 21. Single-Step 6.2Ω LOAD Figure 23. Single-Step 50Ω LOAD www.fairchildsemi.com ...
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... Typical Performance Characteristics Unless otherwise specified 3.6V. IN VSEL Transitions Figure 24. Single-Step from Forced PWM (MODE1=0), R LOAD Figure 26. Single–Step from Auto PWM/PFM (MODE1=1), R LOAD © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 (Continued) = 50Ω = 50Ω 14 Figure 25. Single Step 6.2Ω LOAD www.fairchildsemi.com ...
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... N-channel MOSFET from VOUT to GND. V LOAD Short Circuit and Over-Current Fault Response Figure 27. Metallic Short Applied at VOUT Figure 29 660mΩ LOAD © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 (Continued) = 3.6V, initial V = 1.35V, initial I IN OUT Figure 28. Metallic Short Applied at VOUT Figure 30 ...
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... Typical Performance Characteristics Unless otherwise specified 3.6V. IN Figure 31. SW-Node Jitter (Infinite Persistence 200mA LOAD Figure 33. Soft-Start, R © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 (Continued) Figure 32. SW-Node Jitter, External Synchronization (10) 0.1 Figure 34 50Ω LOAD 16 (Infinite Persistence 200mA ...
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... V . OUT Note: 13. Option 02 maximum voltage is 1.4375V (see Table 3). © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Power-up, EN, and Soft-start All internal circuits remain de-biased and the very low quiescent current state until the following are true: 1 ...
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... Table 3. VSEL vs. VOUT for Options 00, 02, 03, 06 © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 VOUT 02 06 0.7500 1.1875 0.7625 1.2000 0.7750 1.2125 0.7875 1.2250 0.8000 1.2375 ...
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... To achieve this, the regulator turns on the low-side MOSFET to © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 “create demand” for a pulse if no pulse had been required for 40μs. The minimum frequency limit circuit takes effect with load currents below about 3.5mA. Above that load point, the natural PFM period is less than 40μ ...
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... Figure 37 shows single-step transition timing. t time it takes the regulator to settle to within 2% of the new © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 setpoint and is typically 7μs for a full-range transition (from 00000 to 11111 for 6-bit DAC options). The PWROK bit, ...
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... CONTROL2 Table Register Addresses © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Slave Address In Table 10, A1 and A0 are according to the Ordering Information table on page Table 10. I Bus Timing As shown in Figure 39, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. ...
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... S Slave Address 7 bits S Slave Address 0 © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 Read and Write Transactions The following figures outline the sequences for data read and write. Bus control is signified by the shading of the packet, defined as Slave Drives Bus All addresses and data are MSB first. ...
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... Changing this bit changes the behavior of the converter, as described below. Disabled. Converter logic ignores changes made to this bit. Bit can be written to and read-back Read-only . Writing to this bit through I Table 13. Bit Type Definitions for Table 12. © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0 Option OUT ...
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... OUT 110 slews at 9.60mV/ μ s during positive V V OUT A 111 Positive V © 2008 Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 . The six LSBs of the 7-bit value for option 07. OUT . The six LSBs of the 7-bit value for option 07. OUT VSEL1 when VSEL is HIGH, and VSEL0 when VSEL is LOW. ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FAN5355 • Rev. 1.0.4 27 www.fairchildsemi.com ...