MT28F004B3VG-10TET Micron, MT28F004B3VG-10TET Datasheet - Page 12

• Manufacturer Part Number: MT28F004B3VG-10TET
• Description: 4Mb SMART 3 BOOT BLOCK FLASH MEMORY
• Manufacturer: Micron

COMMAND EXECUTION
ent operational modes. Each mode allows specific opera-
tions to be performed. Several modes require a sequence
of commands to be written before they are reached. The
following section describes the properties of each mode,
and Table 3 lists all command sequences required to
perform the desired operation.
READ ARRAY
upon power-up and after a RESET. If the device is in any
other mode, READ ARRAY (FFh) must be given to return
to the array read mode. Unlike the WRITE SETUP com-
mand (40h), READ ARRAY does not need to be given
before each individual read access.
IDENTIFY DEVICE
enter the identify device mode. While the device is in this
mode, any READ produces the device ID when A0 is
HIGH and manufacturer compatibility ID when A0 is
LOW. The device remains in this mode until another
command is given.
WRITE SEQUENCE
array. WRITE SETUP (40h or 10h) is given in the first
NOTE: 1. Must follow WRITE or ERASE CONFIRM commands to the CEL to enable Flash array READ cycles.
4Mb Smart 3 Boot Block Flash Memory
F45_2.p65 – Rev. 2, Pub. 3/01
COMMANDS
READ ARRAY
IDENTIFY DEVICE
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WORD/BYTE
WRITE
Commands are issued to bring the device into differ-
IDENTIFY DEVICE (90h) may be written to the CEL to
Two consecutive cycles are needed to write data to the
The array read mode is the initial state of the device
2. IA = Identify Address: 00h for manufacturer compatibility ID; 01h for device ID.
3. ID = Identify Data.
4. SRD = Status Register Data.
5. On x16 (X00) devices BA = Block Address (A12–A17), on x8 (00X) devices BA = Block Address (A13–A17/[A18]).
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
CYCLES
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA
BUS
1
3
2
1
2
2
2
2
Command Sequences
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
SMART 3 BOOT BLOCK FLASH MEMORY
Table 3
CYCLE
12
FIRST
X
X
X
X
X
X
X
X
cycle. The next cycle is the WRITE, during which the write
address and data are issued and V
Writing to the boot block also requires that the RP# pin be
brought to V
the same time V
to write the word or byte. V
the WRITE is completed (SR7 = 1).
(SR7) is at “0,” and the device does not respond to any
commands. Any READ operation produces the status
register contents on DQ0–DQ7. When the ISM status bit
(SR7) is set to a logic 1, the WRITE has been completed,
and the device goes into the status register read mode
until another command is given.
aborted except by a RESET or by powering down the part.
Doing either during a WRITE corrupts the data being
written. If only the WRITE SETUP command has been
given, the WRITE may be nullified by performing a null
WRITE. To execute a null WRITE, FFh must be written
when BYTE# is LOW, or FFFFh must be written when
BYTE# is HIGH. When the ISM status bit (SR7) has been
set, the device is in the status register read mode until
another command is issued.
While the ISM executes the WRITE, the ISM status bit
After the ISM has initiated the WRITE, it cannot be
Micron Technology, Inc., reserves the right to change products or specifications without notice.
90h
70h
B0h
50h
20h
40h
10h
FFh
HH
PP
or that the WP# pin be brought HIGH at
WRITE
WRITE
WRITE
WRITE
READ
READ
is brought to V
SECOND
CYCLE
PP
WA
WA
BA
must be held at V
IA
X
X
PPH
PP
. The ISM now begins
is brought to V
SRD
D0h
D0h
WD
WD
©2001, Micron Technology, Inc.
ID
4Mb
NOTES
PPH
2, 3
5, 6
6, 7
6, 7
4
1
until
PPH
.