MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 16

• Manufacturer Part Number: MT90826AL1
• Description: Quad Digital Switch
• Manufacturer: Zarlink Semiconductor, Inc.

2 Mbps and 4 Mbps mode (DR2=1, DR1=0, DR0=1)
When the 2 Mbps and 4 Mbps mode is selected, the device is configured with 32-input/32-output data streams.
STi0-15/STo0-15 have a data rate of 2 Mbps and STi16-31/STo16-31 have a data rate of 4 Mbps. This mode
allows a maximum non-blocking capacity of 1,536 x 1,536 channels. The MT90826 is capable of rate conversion,
allowing 2 Mbps input to be converted to 4 Mbps output and vice versa.
2 Mbps mode (DR2=1, DR1=1, DR0 =0)
When the 2 Mbps mode is selected, the device is configured with 32-input/32-output data streams each having 32
64 Kbps channels. This mode allows a maximum non-blocking capacity of 1,024 x 1,024 channels.
3.1
The MT90826 provides the frame evaluation inputs, FEi0 to FEi31, to determine different data input delays with
respect to the frame pulse F0i. By using the frame evaluation input select bits (FE0 to FE4) of the frame alignment
register (FAR), users can select one of the thirty-two frame evaluation inputs for the frame alignment measurement.
The internal master clock, which has a fixed relationship with the CLK and F0i depending upon the mode of
operation, is used as the reference timing signal to determine the input frame delays. See Figure 5 for the signal
alignments between the internal and the external master clocks.
A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. Then the
evaluation starts when the SFE bit in the control register is changed from low to high. Two frames later, the
complete frame evaluation (CFE) bit of the frame alignment register changes from low to high to signal that a valid
offset measurement is ready to be read from bits 0 to 9 of the FAR register. The SFE bit must be set to zero before
a new measurement cycle started.
The falling edge of the frame measurement signal (FEi) is evaluated against the falling edge of the frame pulse
(F0i). See Table 7 for the description of the frame alignment register.
3.2
Input frame offset selection allows the channel alignment of individual input streams, which operate at 4.096 Mbps,
8.192 Mbps or 16.384 Mbps, to be shifted against the input frame pulse (F0i). The input offset selection is not
available for streams operated at 2.048 Mbps. This feature is useful in compensating for variable path delays
caused by serial backplanes of variable lengths, which may be implemented in large centralized and distributed
switching systems.
Each input stream has its own delay offset value programmed by the input delay offset registers. Each delay offset
register can control 4 input streams. There are eight delay offset registers (DOS0 to DOS7) to control 32 input
streams. Possible adjustment can range up to +4.5 internal master clock periods forward with resolution of 0.5
internal master clock period. See Table 8 and Table 9 for frame input delay offset programming.
3.3
The MT90826 allows users to advance individual output streams up to 45 ns with a resolution of 15 ns when the
device is in 8 Mbps, 16 Mbps, 4 and 8 Mbps or 16 and 8 Mbps mode. The output delay adjustment is useful in
compensating for variable output delays caused by various output loading conditions. The frame output offset
registers (FOR0 & FOR3) control the output offset delays for each output streams via the programming of the OFn
bits.
See Table 10 and Table 11 for the frame output offset programming.
Serial Input Frame Alignment Evaluation
Input Frame Offset Selection
Output Advance Offset Selection
Zarlink Semiconductor Inc.
MT90826
16
Data Sheet