MT90826AL1 Zarlink Semiconductor, Inc., MT90826AL1 Datasheet - Page 31

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MT90826AL1

Manufacturer Part Number
MT90826AL1
Description
Quad Digital Switch
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet

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10.2
In accordance with the IEEE 1149.1 standard, the MT90826 uses public instructions. The JTAG Interface contains
a three-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the
TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions:
to select the test data register that may operate while the instruction is current, and to define the serial test data
register path, which is used to shift data between TDI and TDO during data register scanning.
Test Data Register
As specified in IEEE 1149.1, the MT90826 JTAG Interface contains three test data registers:
The MT90826 scan register contains 165 bits.
The LSB bit in the device identification register is the first bit clock out.
The Boundary-Scan register
The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path
around the boundary of the MT90826 core logic.
The Bypass Register
The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO.
The Device Identification Register
The device identification register is a 32-bit register with the register contain of:
0000 0000 1000 0010 0110 0001 0100 1011
MSB
Instruction Register
Zarlink Semiconductor Inc.
LSB
MT90826
31
Data Sheet

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