MT9085BPR Zarlink Semiconductor, Inc., MT9085BPR Datasheet - Page 6

• Manufacturer Part Number: MT9085BPR
• Description: 1024 Channels TDM (ST-BUS) to Parallel Bus Access Circuit (PAC)
• Manufacturer: Zarlink Semiconductor, Inc.

MT9085B
2-130
C16i
CKD=0
Serial
Output
S0-S31
Parallel
Input
MCB=0
OE
Parallel
Input
MCB=1
OE
CKD=1
Serial
Output
S0-S31
Parallel
Input
MCB=0
OE
Parallel
Input
MCB=1
OE
Notes:
C
Arrows in the row marked OE indicate the clock edge which latches in the state of the OE pin. C
serial output channel affected by the OE signal. For example, the level on OE clocked in with edge marked C
serial output drivers for stream 1 during channel 1.
X
S
Y
- on the parallel inputs indicates data closed in with the edge shown will be clocked out on Serial Stream Y, Channel X.
Frame Boundary established by F0i
C
Ch. 31, Bit 0
0
S
31
C
C
Ch. 31, Bit 0
Figure 6 - Functional Data I/O Timing in Parallel to Serial Mode (MCA = 1)
0
1
S
S
31
C
1
0
S
31
C
C
0
S
1
S
31
C
1
1
S
0
C
C
C
1
1
1
S
S
S
0
1
2
C
1
S
0
C
C
C
1
1
1
S
S
S
1
0
2
C
1
S
1
C
C
C
1
1
1
S
S
S
2
3
1
C
1
Ch. 0, Bit 7
Ch. 0, Bit 7
S
C
64 Cycles
1
C
C
1
1
1
S
S
S
2
3
C
1
1
S
2
C
C
C
1
1
1
S
S
S
2
3
C
4
1
S
C
2
C
C
1
1
S
1
S
S
3
2
C
4
1
S
3
C
C
1
1
S
S
3
4
C
1
S
X
3
C
C
S
1
1
Y
S
S
written below the arrow indicates the
4
3
1
S
C
1
2
will enable or disable the
S
0
C
C
C
2
2
S
2
S
Ch. 1, Bit 7
S
0
1
C
1
2
Ch. 1, Bit 7
S
C
0
C
C
2
2
S
2
S
S
0
1
C
1
2
S
1
C
2