MT9085BPR Zarlink Semiconductor, Inc., MT9085BPR Datasheet - Page 8

• Manufacturer Part Number: MT9085BPR
• Description: 1024 Channels TDM (ST-BUS) to Parallel Bus Access Circuit (PAC)
• Manufacturer: Zarlink Semiconductor, Inc.

MT9085B
Functional Description
The MT9085 Parallel Access Circuit (PAC) is a 68 pin
monolithic device. It interfaces a parallel 8 bit, time
division, multiplexed bus to 32 or 16 time division
multiplexed serial streams. The device can be
configured to perform either parallel to serial
conversion or serial to parallel conversion. A single
PAC device can handle 1024 channels. The data on
the parallel bus is in a format suitable for interfacing
with the Zarlink MT9080 Switch Matrix Module
(SMX). The data rate on the serial streams can be
selected to be 2.048 or 4.096 Mbit/s.
The serial input/output format conforms to the
ST-BUS requirements when the data rate is 2.048
Mbit/s (see Figure 3). The ST-BUS is a time-division,
multiplexed serial bus with 32, eight bit channels per
frame. Frame boundaries are delineated by the
frame pulse. Data on the serial streams is clocked in
and out with the C16i clock.
When the device is configured for 4.096 Mbit/s data
rate operation, the first 16 (S0-S15) of the 32 serial
streams are used.
multiplexed serial streams is made up of 64
channels. Data is clocked in or out with the C16i
clock.
Parallel To Serial Conversion
The MT9085 can be configured to perform parallel to
serial conversion by tying the MCA input high.
Data on the eight bit parallel bus (P0-P7) is clocked
into the device with the C16i clock. It is clocked out
on the serial streams at either 2.048 Mbit/s (2/4S =0)
or at 4.096 Mbit/s (2/4S=1). See Figures 16, 17 and
19 for timing information.
2-132
0 1 2 3 4 5 6 7
CH. 2
TS64
TS65
TS95
•
•
•
•
•
•
•
•
0 1 2 3 4 5 6 7
CH. 1
TS32
TS33
TS63
Each of the 16 time-division
•
•
•
•
0 1 2 3 4 5 6 7 Bit #
Figure 8 - PAC Operation at 2.048 Mbit/s
TS31
CH. 0
TS0
TS1
•
•
•
•
Parallel to Serial Conversion
Serial to Parallel Conversion
S0
S1
S31
•
•
•
•
PAC
P0
P1
P2
P3
P4
P5
P6
P7
Contiguous channels clocked into the device are
output on the serial streams in an interleaved
manner on each of the serial outputs. For example
when the device is configured for 2.048 Mbit/s data
rate, the first 32 parallel channels clocked into the
device will be clocked out during channel 0 on serial
streams 0 to 31. Channel 1 on serial streams 0 to 31
will contain data from the next 32 timeslots. On any
single serial stream, consecutive output channels
are sourced from every 32nd parallel input channel
(see Figures 6 and 8). When the device is configured
for 4.096 Mbit/s serial output operation, contiguous
channels on the serial streams are sourced from
every 16th parallel input channel.
Data on the eight bit parallel bus is clocked into the
device with the C16 clock. The level asserted on the
MCB input specifies whether the data is clocked into
the device on the falling edge or the rising edge of
C16. The relative phase of the critical edge with
respect to the system frame boundary is defined by
the level asserted on the CKD pin as illustrated in
Figure 16. The flexibility in input timing permits the
PAC to be easily interfaced to the SMX in 1024 and
2048 switching applications. Refer to the applications
section of this data sheet for more details.
The delay through the PAC is approximately one
ST-BUS channel time when the device is operated in
2.048 Mbit/s mode, i.e., any specific channel clocked
into the device will be clocked out one ST-BUS
channel later. In the 4.096 Mbit/s mode, the delay is
equal to eight C4 clock cycles.
Serial output channel timeslots can be tri-stated by
setting OE high during a specific parallel channel
timeslot. The timing for OE is described in Figures 6
and 21. Note that the level asserted on MCB affects
the operation of OE.
TS
0
0
1
2
3
4
5
6
7
TS
1
0
1
2
3
4
5
6
7
TS
31
0
1
2
3
4
5
6
7
TS
32
0
1
2
3
4
5
6
7
TS
33
0
1
2
3
4
5
6
7
TS
63
0
1
2
3
4
5
6
7
TS
64
0
1
2
3
4
5
6
7