74VHC574MTC Fairchild Semiconductor, 74VHC574MTC Datasheet - Page 4

• Manufacturer Part Number: 74VHC574MTC
• Description: IC F/F OCTAL D-TYPE 3ST 20-TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74VHCr
• Type: D-Type Busr

Specifications of 74VHC574MTC

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 180MHz
• Delay Time - Propagation: 5.6ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 8mA, 8mA
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Number Of Circuits: 8
• Logic Family: 74VHC
• Logic Type: D-Type Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 16.7 ns
• High Level Output Current: - 8 mA
• Low Level Output Current: 8 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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t
t
t
t
t
t
t
t
f
C
C
C
t
t
t
t
PLH
PHL
PZL
PZH
PLZ
PHZ
OSLH
OSHL
MAX
W
W
S
H
AC Electrical Characteristics
Note 4: Parameter guaranteed by design. t
Note 5: C
operating current can be obtained by the equation: I
can be calculated by the equation: C
AC Operating Requirements
IN
OUT
PD
Symbol
Symbol
(H)
(L)
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
Propagation Delay
Time (CP to O
3-STATE Output
Enable Time
3-STATE Output
Disable Time
Output to
Output Skew
Maximum Clock
Frequency
Input
Capacitance
Output
Capacitance
Power Dissipation
Capacitance
Minimum Pulse Width (CP)
Minimum Set-Up Time
Minimum Hold Time
Parameter
n
Parameter
)
PD
(total)
OSLH
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
20
V
(V)
r
r
r
r
r
r
r
r
r
|t
CC
r

PLH max
CC
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
8n.
(opr.)

3.3
5.0
3.3
5.0
3.3
5.0
Min
130
t
80
50
85
PLH min
C
V
PD
(V)
r
r
r
r
r
r
CC
* V
0.3
0.5
0.3
0.5
0.3
0.5
|; t
CC
T
OSHL
A
* f
11.0
10.7
11.0
Typ
125
180
115
8.5
5.6
7.1
8.2
5.9
7.4
7.1
75
28
4
6
IN
25
4

Min
5.0
5.0
3.5
3.5
1.5
1.5
|t
q
PHL max
I
C
CC
/8 (per F/F). The total C
Max
13.2
16.7
10.6
12.8
16.3
11.0
15.0
10.1
8.6
9.0
1.5
1.0
10

T
t
A
PHL min
Typ
25
q
|
T
C
A
Min
110
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
65
45
75

40
Max
PD
q
C to
when n pcs. of the Octal D Flip-Flop operates
Max
15.5
19.0
10.0
12.0
15.0
18.5
10.5
12.5
17.0
11.5

1.5
1.0
10
85
q
C
T
A
Min
5.0
5.0
3.5
3.5
1.5
1.5

Units
MHz
40
pF
pF
pF
ns
ns
ns
ns
ns
ns
q
C to
R
R
(Note 4)
V
V
(Note 5)

Max
L
L
CC
CC
85
q
1 k
1 k
Conditions
C
Open
5.0V
:
:
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Units
ns
ns
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
50 pF
50 pF
15 pF
50 pF
15 pF
50 pF