MM74HCT574MTC Fairchild Semiconductor, MM74HCT574MTC Datasheet - Page 5

• Manufacturer Part Number: MM74HCT574MTC
• Description: IC FLIP FLOP OCT D 3ST 20-TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74HCTr
• Type: D-Type Busr

Specifications of MM74HCT574MTC

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 33MHz
• Delay Time - Propagation: 18ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 7.2mA, 7.2mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Logic Family: HCT
• Technology: CMOS
• Number Of Bits: 8
• Number Of Elements: 1
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Operating Supply Voltage (typ): 5V
• Package Type: TSSOP
• Propagation Delay Time: 38ns
• Low Level Output Current: 7.2mA
• High Level Output Current: -7.2mA
• Frequency (max): 28MHz
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

f
t
t
t
t
t
t
t
t
t
MAX
PHL
PLH
PZH
PZL
PHZ
PLZ
W
S
H
AC Electrical Characteristics
V
AC Electrical Characteristics
V
f
t
t
t
t
t
t
t
t
t
t
t
C
C
C
Note 6: C
Symbol
MAX
PHL
PLH
PZH
PZL
PHZ
PLZ
THL
TLH
W
S
H
CC
CC
Symbol
IN
OUT
PD
5.0V, t
5.0V
PD
Maximum Clock Frequency
Maximum Propagation Delay
to Output
Maximum Enable Propagation Delay
Control to Output
Maximum Disable Propagation Delay
Control to Output
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
determines the no load power consumption, P
Maximum Clock Frequency
Maximum Propagation Delay
Clock to Output
Maximum Enable Propagation
Delay Control to Output
Maximum Disable Propagation
Delay Control to Output
Maximum Output
Rise and Fall Time
Minimum Clock Pulse Width
Minimum Setup Time Data to Clock
Minimum Hold Time Clock to Data
Maximum Input Capacitance
Maximum Output Capacitance
Power Dissipation Capacitance
(Note 6)
r
r
10%, t
t
f
6 ns, T
r
Parameter
Parameter
t
f
6 ns (unless otherwise specified)
A
25
q
C
C
C
R
C
R
C
OC
OC
C
C
R
C
R
L
L
L
L
L
L
L
L
L
L
L
D
50 pF
50 pF
1 k
50 pF
1 k
50 pF
V
GND
45 pF
45 pF
1 k
45 pF
1 k
C
MM74HCT574
CC
:
:
MM74HCT574
PD
:
:
Conditions
V
CC
Conditions
2
f

I
CC
5
V
CC
, and the no load dynamic current consumption, I
T
Typ
18
22
15

58
A
6
6
5
1
25
q
C
33
30
30
30
12
15
12
10
20
5
Typ
60
17
19
14
T
A

Guaranteed Limits
40 to 85
28
38
38
38
15
20
15
10
20
6
Guaranteed Limit
q
C T
33
27
28
25
15
12
5
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A
S

55 to 125
C
23
45
45
45
18
24
18
10
20
PD
8
V
CC
f
Units
MHz
q

C
ns
ns
ns
ns
ns
ns
I
CC
Units
MHz
.
pF
pF
pF
ns
ns
ns
ns
ns
ns
ns