74AC175SC Fairchild Semiconductor, 74AC175SC Datasheet - Page 2

• Manufacturer Part Number: 74AC175SC
• Description: IC FLIP FLOP D TYPE QUAD 16SOIC
• Manufacturer: Fairchild Semiconductor
• Series: 74ACr
• Type: D-Type Busr

Specifications of 74AC175SC

• Function: Master Reset
• Output Type: Differential
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Frequency - Clock: 244MHz
• Delay Time - Propagation: 7ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Number Of Circuits: 4
• Logic Family: 74AC
• Logic Type: D-Type Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 13 ns
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Supply Voltage (max): 6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©1988 Fairchild Semiconductor Corporation
74AC175, 74ACT175 Rev. 1.4
Logic Symbol
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
IEEE/IEC
Figure 1.
2
Functional Description
The AC/ACT175 consists of four edge-triggered D-type
flip-flops with individual D inputs and Q and Q outputs.
The Clock and Master Reset are common. The four flip-
flops will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master
Reset (MR) will force all Q outputs LOW and Q outputs
HIGH independent of Clock or Data inputs. The AC/
ACT175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
t
t
n
n+1
Inputs @ t
= Bit Time before Clock Pulse
= Bit Time after Clock Pulse
D
H
L
n
n
, MR = H
Q
Outputs @ t
H
L
n
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n+1
Q
H
L
n