isl6307b Intersil Corporation, isl6307b Datasheet - Page 21

• Manufacturer Part Number: isl6307b
• Description: 6-phase Vr11 Pwm Controller With 8-bit Vid Code Capable Of Precision Rds On Or Dcr Differential Current Sensing For Applications In Which Supply Voltage Is Higher Than 5v
• Manufacturer: Intersil Corporation

the controller will execute 12.5mV changes six times per
cycle until VID and DAC are equal. It is for this reason that it
is important to carefully control the rate of VID stepping in
1-bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R
based voltage regulator. The selection of R
the desired offset as detailed above in Output-Voltage Offset
Programming. The selection of C
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every T
of R
Equation 13.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
C
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
REF
REF
R
FAULT LOGIC
CIRCUIT
SOFT-START
REF
and C
POR
ISL6307B INTERNAL CIRCUIT
AND
VID
=
SENSITIVE ENABLE (EN) FUNCTION
REF
REF
T
, the relationship between the time constant
VID
network and T
and C
COMPARATOR
ENABLE
REF
21
+
-
0.875V
+
0.875V
-
is required for an ISL6307B
REF
VID
is based on the time
is given by
EXTERNAL CIRCUIT
VCC
EN_VTT
EN_PWR
REF
10kΩ
910Ω
is based on
+12V
(EQ. 13)
ISL6307B
following input conditions must be met before the ISL6307B
is released from shutdown mode.
When all conditions above are satisfied, ISL6307B begins
the soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6307B reads the VID
code at VID input pins. If the VID code is valid, ISL6307B will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6307B will shut down. Cycling Vcc, EN_PWR
or EN_VTT is needed to restart.
Soft-start
ISL6307B based VR has 4 periods during soft-start, as
shown in Figure 11. After Vcc, EN_VTT and EN_PWR reach
their POR and enable thresholds, The controller will have
fixed delay period TD1. After this delay period, the VR will
begin first soft-start ramp until the output voltage reaches
1.1V, Vboot voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period, TD3. At the end of
TD3 period, ISL6307B will read the VID signals. If the VID
code is valid, ISL6307B will initiate the second soft-start
ramp until the voltage reaches the VID voltage minus offset
voltage.
The soft-start time is the sum of the 4 periods as shown in
the following equation.
TD1 is the fixed delay with typical value as 1.36ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to valid the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
During TD2 and TD4, ISL6307B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
T
1. The bias voltage applied at VCC must reach the internal
2. The ISL6307B features an enable input (EN_PWR) for
3. The voltage on EN_VTT must be higher than 0.875V to
SS
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307B is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6307B will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications).
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6307B in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6307B becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6307B with the
ISL66xx family of Intersil MOSFET drivers, which require
12V bias.
enable the controller. This pin is typically connected to the
output of VTT VR.
=
TD1
+
TD2
+
TD3
+
TD4
March 9, 2006
(EQ. 14)
FN9225.0