isl6307b Intersil Corporation, isl6307b Datasheet - Page 29

• Manufacturer Part Number: isl6307b
• Description: 6-phase Vr11 Pwm Controller With 8-bit Vid Code Capable Of Precision Rds On Or Dcr Differential Current Sensing For Applications In Which Supply Voltage Is Higher Than 5v
• Manufacturer: Intersil Corporation

In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
The optional capacitor C
noise away from the PWM comparator (see Figure 20). Keep
a position available for C
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R
value of R
oscilloscope until no further improvement is noted. Normally,
C
Equation 34 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 21, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f
higher if desired. Choosing f
cause problems with too much phase shift below the system
bandwidth.
C
FIGURE 21. COMPENSATION CIRCUIT FOR ISL6307B BASED
will not need adjustment. Keep the value of C
C
R
1
1
C
while observing the transient performance on an
CONVERTER WITHOUT LOAD-LINE
REGULATION
R
FB
R
C
C
2
2
2
, is sometimes needed to bypass
, and be prepared to install a high-
C
C
HF
29
HF
to be lower than 10f
HF
IDROOP
. This pole can be used for
COMP
VDIFF
= 10f
FB
C
. Slowly increase the
P-P
0
, but it can be
is the peak-to-
C
0
from
0
, of the
can
ISL6307B
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 35, R
compensation components are then selected according to
Equation 35.
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
pulsating voltage at the phase nodes. The output filter also
must provide the transient energy until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response. The output capacitor must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
R
C
C
R
C
1
1
2
C
C
=
=
=
=
=
R
---------------------------------------- -
-------------------------------------------------------------------- -
(
-----------------------------------------------------------------------
- 0.75 V
-------------------------------------------------------------------- -
(
2π
2π
LC C ESR
0.75V
FB
V
PP
)
)
2
---------------------------------------- -
2
–
R
f
MAX
f
LC C ESR


0
0
FB
2π
IN
IN
f
C ESR
f
HF
(
0.75V
HF


FB
(
–


2πf


. Capacitors are characterized according to
2
2πf
f
LCR
0
LCR
is selected arbitrarily. The remaining
(
HF
f
)
IN
HF
HF
)
FB
LCR
FB
LC 1
)
LC 1
V
V
–
P-P
–
P-P
FB




P-P
is the peak-to-
March 9, 2006
(EQ. 35)
FN9225.0