isl6312a Intersil Corporation, isl6312a Datasheet - Page 27

• Manufacturer Part Number: isl6312a
• Description: Four-phase Buck Pwm Controller With Integrated Mosfet Drivers For Intel Vr10, Vr11, And Amd Applications
• Manufacturer: Intersil Corporation

.
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 26, 27, 28 and 29. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of 125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
at room temperature. See Layout Considerations paragraph
for thermal transfer improvement suggestions.
When designing the ISL6312A into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 30 and 31, respectively.
In Equations 30 and 31, P
power loss and P
loss; the gate charge (Q
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I
quiescent current with no load at both drive outputs; N
N
respectively; N
I
without capacitive load and is typically 75mW at 300kHz.
P
P
Q*
P
P
I
Q2
UP 4 ,
DR
Qg_TOT
Qg_Q2
Qg_Q1
VCC product is the quiescent power of the controller
are the number of upper and lower MOSFETs per phase,
=
≈
⎛
⎝
r
DS ON
3
-- - Q
2
=
=
=
⋅
(
Q
3
-- - Q
2
P
G1
G2
⋅
Qg_Q1
PHASE
)
⋅
⋅
G1
⋅
d
N
Qg_Q2
PVCC F
⋅
Q1
⋅
PVCC F
+
⎛
⎜
⎝
I
----- -
+
N
P
is the number of active phases. The
M
Qg_Q2
Q
⎞
⎟
⎠
G1
⋅
is the total lower gate drive power
2
G2
Qg_Q1
+
SW
⋅
and Q
I
--------- -
⋅
PP
12
27
N
SW
⋅
+
2
Q2
N
I
Q
Q2
⋅
is the total upper gate drive
⎞ N
⎠
G2
N
⋅
⋅
VCC
Q1
⋅
) is defined at the
N
Q
PHASE
PHASE
⋅
is the driver total
N
PHASE
⋅
F
Qg_TOT
SW
+
I
Q
(EQ. 30)
(EQ. 31)
, due to
Q1
(EQ. 29)
and
ISL6312A
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P
P
power will be dissipated by the external gate resistors (R
and R
the MOSFETs. Figures 16 and 17 show the typical upper and
lower gate drives turn-on transition path. The total power
dissipation in the controller itself, P
estimated as:
P
P
P
R
P
DR_UP
FIGURE 17. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
FIGURE 16. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
DR
DR_UP
DR_LOW
PVCC
EXT1
BOOT
PVCC
=
G2
P
=
, and in the boot strap diode, P
) and the internal gate resistors (R
=
PHASE
DR_UP
=
R
P
---------------------
=
R
⎛
⎜
⎝
R
G1
LO2
Qg_Q1
--------------------------------------
R
BOOT
HI2
⎛
⎜
⎝
R
R
3
HI1
--------------------------------------
R
+
LO1
HI1
HI2
+
R
-------------
R
N
+
DR_UP
P
GI1
HI1
R
Q1
DR_LOW
R
+
HI2
EXT1
R
LGATE
EXT2
UGATE
, the lower drive path resistance,
+
+
--------------------------------------- -
R
+
LO1
--------------------------------------- -
R
P
R
LO2
BOOT
EXT2
R
R
G2
R
+
LO1
R
G
DR
G1
R
+
LO2
G
EXT1
R
+
R
, can be roughly
=
C
EXT2
BOOT
GI2
(
GD
R
R
C
I
C
Q
GI1
GD
G2
GS
⎞ P
⎟
⎠
C
⋅
GI1
⋅
GS
VCC
⎞ P
⎟
⎠
+
. The rest of the
---------------------
⋅
S
Qg_Q1
R
-------------
---------------------
N
and R
Qg_Q2
S
3
GI2
Q2
)
2
D
August 1, 2007
D
GI2
Q2
C
(EQ. 32)
FN9290.3
DS
Q1
C
) of
G1
DS