isl6590dr Intersil Corporation, isl6590dr Datasheet - Page 14

• Manufacturer Part Number: isl6590dr
• Description: Digital Multi-phase Pwm Controller For Core-voltage Regulation
• Manufacturer: Intersil Corporation

ISL6580 Calibration
Prior to calibration, the status of each ISL6580 is checked.
The input supply voltage is checked by polling the status of
the under-voltage lockout in the status registers of the
ISL6580s. Other faults are also checked. If a fault is
detected during or after calibration, the system state may be
frozen while fault processing takes over to resolve the error.
To calibrate the voltage ADC, the VID is set to the same
voltage as the external VID setting. Voltage ADC calibration
is initiated by setting the device that is hard wired for
Regulation mode into calibration mode. This should be
device #1. During calibration, any offset voltage internal to
the ADC is output on the ERR serial line. The error is stored
in the non-volatile memory. Then the ISL6590 changes
themode of the ISL6580 to normal operation and calibration
is complete.
05h
06h
09-1Fh
00h
01h
02h
03h
04h
MHz Power IC Configuration Process
First the master will initiate “config call” by sending a “10’h00” address
All of the slaves should “ACK” because every MHz Power IC register contains 0” after reset
The ID is then sent out during the data cycle.
The process is repeated until all (N) of the devices are configured.
SCLK
SCLK
SDATA
SDATA
PWM1
PWM1
("ID" register enable)
("ID" register enable)
BSB ID
TABLE 10. SERIAL BUS ID MAPPING
Start
Start
"0000000000"
"0000000000"
“config call”
Power IC 1
Power IC 2
Power IC 3
Power IC 4
Power IC 5
Power IC 6
Reserved
Address Cycle
Address Cycle
10 clocks
10 clocks
Configcall
Configcall
14
DESCRIPTION
FIGURE 11. ENUMERATION TIMING DIAGRAM
Ack
Ack
Directio
Directio
R/W
R/W
n
n
ISL6590
ID for Power IC 1
ID for Power IC 1
MHz Power IC 1 ID register enable
MHz Power IC 1 ID register enable
ISL6580 Softstart
The system is slowly brought out of the no output voltage
open loop state by sending a small PWM pulse width to the
ISl6580s. A fixed time period and step size is used to bring
the output voltage into the lower range of the voltage ADC.
Once the voltage ADC begins reading voltage, a fixed V
step size is used (25mV). After each V
performed, the output voltage must settle within a +/-
(V
stepping to the next output voltage setting. The stepping
continues until the final voltage is reached.
Power On Reset
The ISL6590 controller performs a Power On Reset function
internally. It holds all internal logic in a reset state until the
Vdd (3.3V) exceeds a threshold. While in the reset state all
PWM and NDRIVE signals are held at ground and all
MOSFETs are OFF.
Duty Cycle Limit
The ISL6590 limits the on time of the upper FETs. The
system designer can set the maximum ON time with
PowerCode software The value is put in as a percentage. If
the duty cycle reaches this percentage, the top side FET
turns off until the next cycle.
step
Data Cycle
Data Cycle
8 Clocks
8 Clocks
/2) mV window of the specified VID voltage before
Ack
Ack
Stop
Stop
Repeat for N-1 devices
Repeat for N-1 devices
step
step is
step