isl6590dr Intersil Corporation, isl6590dr Datasheet - Page 5

• Manufacturer Part Number: isl6590dr
• Description: Digital Multi-phase Pwm Controller For Core-voltage Regulation
• Manufacturer: Intersil Corporation

Pin Descriptions
1
2-7
8, 21, 39, 57
9
10, 25, 42,
44, 54
11
12
13
14
15, 18, 22,
26, 30, 34
16, 19, 23,
27, 31, 35
17, 20, 24,
28, 32, 36
29
33, 48, 50,
51
37, 38, 40,
41
43
45
46
47
49
52
53
55
56
58
59
60
61
62
63
64
65
PIN NO.
PLL_ANA_VDD
PLL_ANA_VSS
PLL_DIG_VDD
PLL_DIG_VSS
NDRIVE[1:6]
VDD_CORE
PLL Bypass
EXT_Reset
PIN NAME
OSC_OUT
PLL_Filter
PWM[1:6]
TEST[1:4]
SYSCLK
PWRGD
VDD_IO
OSC_IN
OUTEN
VID[0:5]
IDIG[1:6]
SDATA
MCLK
ATRH
SCLK
ATRL
MDO
MCS
SOC
GND
ERR
ARX
ATX
MDI
NC
5
Analog Input Filter cap for PLL.
Input/Output System clock which runs at a 133.3MHz rate used to clock the ISL6580. This is generated by the
Input/Output Controller serial interface for communication, monitoring, and configuration data between the
Ground
Ground
Ground
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
N/A
Output enable high input signal used to command the regulator on and a low input signal turns
the regulator off.
Voltage identification (6 bit). Programs Vout regulation voltage.
IC internal core supply voltage (1.8 VDC logic).
Power Good high output signal to indicate the regulator output voltage is within the specified
range. A low signal indicates the voltage is not within range.
IC I/O input supply voltage (3.3 VDC logic).
EEPROM external memory clock, data is clocked out of the IC on the rising edge and data is
clocked into the ISL6580 IC on the falling edge. Compliant with SPI™ EEPROMs.
EEPROM external memory data output. Compliant with SPI EEPROMs
EEPROM external memory data input. Compliant with SPI EEPROMs.
EEPROM external memory chip select (Active low). Compliant with SPI EEPROMs.
Low side drive signal used to initiate the ISL6580 to turn on the LSFET.
PWM performs pulse width modulation which is used to turn on the ISL6580’s power devices.
Current A/D data serial 7-bit digital word (MSB first). The first bit is a start bit (Start = 1). The
remaining 6 bits represent the sampled peak current in the drain of the particular ISL6580
P-Channel HSFET. (IDIG word transmission is triggered by the falling edge of the PWM signal.)
IDIG is an input that is received at SYSCLK/2, normally 66.6MHz.
Voltage identification (6 bit). Programs Vout regulation voltage.
Test pins for part evaluation
These pins have not been bonded out.
internal PLL circuit to create a 4x frequency multiply of the OSC_IN frequency.
Serial data transmitted at a 66MHz (or SYSCLK/2) rate. This 6 bit voltage error is feedback into
the control loop and used to regulate the output voltage.
Start of Conversion signal initiated by the ISL6580’s Voltage A/D to create the ERR signal.
Active Transient Response Low input signal from the ISL6580 indicating a voltage overshoot on
the converter output.
Active Transient Response High input signal from the ISL6580 indicating a voltage droop on the
converter output.
ISL6580 and ISL6590 controller.
Serial digital bus clock supplied for the 16.67MHz clocking that accompanies SDATA via the
Backside serial bus.
Asynchronous Serial Interface Transmit
Asynchronous Serial Interface Receive
Only used if part is using a crystal to generate the system clock.
Requires a 33.33MHz oscillator or crystal which is used to generate system clock.
Digital Ground for the 4X clock multiplier PLL
Test mode to bypass PLL input to core.
1.8V power supply for the 4X clock multiplier PLL clock tree driver (1.8 VDC logic)
Analog Ground for the 4X clock multiplier PLL.
1.8V power supply for the 4X clock multiplier PLL (1.8 VDC logic).
Paddle IC Ground
ISL6590
PIN DESCRIPTION
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