pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 104

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
17.3
17.4
AC SPECIFICATIONS
1. See Figure 17-1 PCI Signal Timing Measurement Conditions.
2. All primary interface signals are synchronized to P_CLK. All secondary interface
signals are synchronized to S_CLKOUT.
3. Point-to-point signals are P_REQ_L, S_REQ_L[7:0], P_GNT_L, S_GNT_L[7:0],
HSLED, HS_SW_L, HS_EN, and ENUM_L. Bused signals are P_AD, P_BDE_L, P_PAR,
P_PERR_L, P_SERR_L, P_FRAME_L, P_IRDY_L, P_TRDY_L, P_LOCK_L,
P_DEVSEL_L, P_STOP_L, P_IDSEL, S_AD, S_CBE_L, S_PAR, S_PERR_L,
S_SERR_L, S_FRAME_L, S_IRDY_L, S_TRDY_L, S_LOCK_L, S_DEVSEL_L, and
S_STOP_L.
4. REQ_L signals have a setup of 12 and GNT_L signals have a setup of 10.
66MHZ TIMING
Symbol
Tsu
Tsu(ptp)
Th
Tval
Tval(ptp)
Ton
Toff
Symbol
T
T
T
T
T
SKEW
DELAY
CYCLE
HIGH
LOW
Figure 17-1
Parameter
SKEW among S_CLKOUT[9:0]
DELAY between PCLK and S_CLKOUT[9:0]
P_CLK, S_CLKOUT[9:0] cycle time
P_CLK, S_CLKOUT[9:0] HIGH time
P_CLK, S_CLKOUT[9:0] LOW time
Parameter
Input setup time to CLK – bused signals
Input setup time to CLK – point-to-point
Input signal hold time from CLK
CLK to signal valid delay – bused signals
CLK to signal valid delay – point-to-point
Float to active delay
Active to float delay
PCI Signal Timing Measurement Conditions
Page 104 of 108
1,2
1,2
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
1,2
1,2,3
1,2,3
1,2,3
1,2,3
Condition
20pF load
Min.
3
5
0
2
2
2
-
66 MHz
APRIL 2006 – Revision 2.02
Max.
-
-
-
6
6
-
14
Min.
6
6
0
3.14
15
Min.
7
10, 12
0
2
2
2
-
33 MHz
Max.
0.250
5.07
30
4
PI7C8150B
Max.
-
-
-
11
12
-
28
Units
ns
Units
ns