pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 91

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.43
14.1.44
RETRY COUNTER REGISTER – OFFSET 78h
SECONDARY BUS MASTER TIMEOUT COUNTER – OFFSET 80h
Bit
9
10
11
15:12
Bit
31:0
Bit
15:0
Function
Enable Long
Request
Enable
Secondary To
Hold Request
Longer
Enable Primary
To Hold Request
Longer
Reserved
Function
Retry Counter
Function
Secondary
Timeout
Type
R/W
R/W
R/W
R/O
Type
R/W
Type
R/W
Page 91 of 108
Description
Controls PI7C8150B’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C8150B’s ability to enable the secondary bus to hold
requests longer.
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Control’s PI7C8150B’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Reserved. Returns 0 when read. Reset to 0.
Description
Holds the maximum number of attempts that PI7C8150B will try
before reporting retry timeout. Retry count set at 2
Default is 0100 0000h.
Description
There are 2 control settings for the secondary bus master timeout
counter. Bit[25] offset 3Ch can set the counter to either 2
clocks. Bit[15:0] offset 80h may control the granularity down to 1
PCI clock (from 0h to FFFFh). Both controls will over-write each
other, with the last write value being used for the initial value loaded
into the timeout counter. The timeout counter will start after the last
data (if less than a cache line) or the first cache line data (if more than
one cache line) is completed to the bridge. Once the timeout counter
expires, the corresponding data in the buffer will be discarded.
Reset to 8000h.
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
24
PCI clocks.
PI7C8150B
10
or 2
15