pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 33

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.7.3
3.7.4
PI7C8150B forwards Type 1 to Type 0 configuration read or write transactions as delayed
transactions. Type 1 to Type 0 configuration read or write transactions are limited to a
single 32-bit data transfer.
TYPE 1 TO TYPE 1 FORWARDING
Type 1 to Type 1 transaction forwarding provides a hierarchical configuration mechanism
when two or more levels of PCI-to-PCI bridges are used.
When PI7C8150B detects a Type 1 configuration transaction intended for a PCI bus
downstream from the secondary bus, PI7C8150B forwards the transaction unchanged to the
secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command
or to a special cycle transaction by a downstream PCI-to-PCI bridge. Downstream Type 1
to Type 1 forwarding occurs when the following conditions are met during the address
phase:
PI7C8150B also supports Type 1 to Type 1 forwarding of configuration write transactions
upstream to support upstream special cycle generation. A Type 1 configuration command
is forwarded upstream when the following conditions
are met:
The PI7C8150B forwards Type 1 to Type 1 configuration write transactions as delayed
transactions. Type 1 to Type 1 configuration write transactions are limited to a single data
transfer.
SPECIAL CYCLES
The Type 1 configuration mechanism is used to generate special cycle transactions in
hierarchical PCI systems. Special cycle transactions are ignored by acting as a target and
are not forwarded across the bridge. Special cycle transactions can be generated from Type
1 configuration write transactions in either the upstream or the down-stream direction.
The lowest two address bits are equal to 01b.
The bus number falls in the range defined by the lower limit (exclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
The bus command is a configuration read or write transaction.
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive) in the
secondary bus number register and the upper limit (inclusive) in the subordinate bus
number register.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
Page 33 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B