pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 26

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.5.4
3.5.5
Table 3-3. Write Transaction Disconnect Address Boundaries
If the initiator repeats the write transaction before the data has been transferred to the
target, PI7C8150B returns a target retry to the initiator. PI7C8150B continues to return a
target retry to the initiator until write data is delivered to the target, or until an error
condition is encountered. When the write transaction is repeated, PI7C8150B does not
make a new entry into the delayed transaction queue. Section 3.8.3.1 provides detailed
information about how PI7C8150B responds to target termination during delayed write
transactions.
PI7C8150B implements a discard timer that starts counting when the delayed write
completion is at the head of the delayed transaction completion queue.
The initial value of this timer can be set to the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard
timer expires, PI7C8150B discards the delayed write completion from the delayed
transaction completion queue. PI7C8150B also conditionally asserts P_SERR_L
(see Section 6.4).
WRITE TRANSACTION ADDRESS BOUNDARIES
PI7C8150B imposes internal address boundaries when accepting write data. The aligned
address boundaries are used to prevent PI7C8150B from continuing a transaction over a
device address boundary and to provide an upper limit on maximum latency. PI7C78150
returns a target disconnect to the initiator when it reaches the aligned address boundaries
under conditions shown in Table 3-3.
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C8150B continues to accept posted memory write transactions as long as space for at
least one DWORD of data in the posted write data buffer remains. If the posted write data
buffer fills before the initiator terminates the write transaction, PI7C8150B returns a target
disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in the delayed
transaction queue exists. Therefore, several posted and delayed write transactions can exist
in data buffers at the same time. See Chapter 6 for information about how multiple posted
and delayed write transactions are ordered.
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
Type of Transaction
Delayed Write
Posted Memory Write
Posted Memory Write
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
bit = 0
Condition
All
Memory write disconnect control
Memory write disconnect control
bit = 1
Cache line size ≠ 1, 2, 4, 8, 16
Cache line size = 1, 2, 4, 8, 16
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Aligned Address Boundary
Disconnects after one data transfer
4KB aligned address boundary
Disconnects at cache line boundary
4KB aligned address boundary
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
APRIL 2006 – Revision 2.02
PI7C8150B