pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 39

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
3.8.4.2
For delayed read transactions:
For posted write transactions:
TARGET DISCONNECT
PI7C8150B returns a target disconnect to an initiator when one of the following conditions
is met:
The delayed transaction queue is full, and the transaction cannot be queued.
A transaction with the same address and command has been queued.
A locked sequence is being propagated across PI7C8150B, and the write transaction is
not a locked transaction.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
The transaction is being entered into the delayed transaction queue.
The read request has already been queued, but read data is not yet available.
Data has been read from target, but it is not yet at head of the read data queue or a
posted write transaction precedes it.
The delayed transaction queue is full, and the transaction cannot be queued.
A delayed read request with the same address and bus command has already been
queued.
A locked sequence is being propagated across PI7C8150B, and the read transaction is
not a locked transaction.
PI7C78150B is currently discarding previously pre-fetched read data.
The target bus is locked and the write transaction is a locked transaction.
Use more than 16 clocks to accept this transaction.
The posted write data buffer does not have enough space for address and at least one
DWORD of write data.
A locked sequence is being propagated across PI7C8150B, and the write transaction is
not a locked transaction.
When a target retry is returned to the initiator of a delayed transaction, the initiator
must repeat the transaction with the same address and bus command as well as the data
if it is a write transaction, within the time frame specified by the master timeout value.
Otherwise, the transaction is discarded from the buffers.
PI7C8150B hits an internal address boundary.
Page 39 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B