pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 16

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
2.2.4
MISCELLANEOUS SIGNALS
Name
S_CLKOUT[9:0]
Name
MSK_IN /
ASYNC_CLKIN
P_VIO
S_VIO
BPCCE
Pin #
42, 41, 39, 38, 36,
35, 33, 32, 30, 29
Pin #
126
124
135
44
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ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
Pin #
M3, M2, N1,
L4, L3, M1, L2,
L1, K3, K2
Pin #
K15
K14
G14
N2
Type
Type
O
I
I
I
I
Description
Secondary Clock Output: Provides secondary clocks
phase synchronous with the P_CLK in synchronous
mode.
When these clocks are used, one of the clock outputs
must be fed back to S_CLKIN. Unused outputs may be
disabled by:
1. Writing the secondary clock disable bits in the
configuration space
2. Using the serial disable mask using the GPIO pins and
MSK_IN
3. Terminating them electrically.
In asynchronous mode, S_CLKOUT[5:0] are derived
from MSK_IN / ASYNC_CLKIN (please see CFG66 /
SCAN_EN_H / CLK_RATE pin description).
Description
This is a multiplexed pin that is MSK_IN in
synchronous mode and ASYNC_CLK_IN in
asynchronous mode. This pin has a weak internal pull-
down resistor.
MSK_IN - Secondary Clock Disable Serial Input
(synchronous mode): This pin is used by PI7C8150B to
disable secondary clock outputs. The serial stream is
received by MSK_IN, starting when P_RESET is
detected deasserted and S_RESET_L is detected as
being asserted. The serial data is used for selectively
disabling secondary clock outputs and is shifted into the
secondary clock control configuration register. This pin
can be tied LOW to enable all secondary clock outputs
or tied HIGH to drive all the secondary clock outputs
HIGH.
ASYNC_CLKIN – Secondary Clock Input
(asynchronous mode): The asynchronous clock for the
secondary interface should be connected to this pin in
asynchronous mode. S_CLKOUT[9:0] will be derived
from ASYNC_CLKIN.
Primary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the primary bus. P_VIO
must be tied to 3.3V only when all devices on the
primary bus use 3.3V signaling. Otherwise, P_VIO is
tied to 5V.
Secondary I/O Voltage: This pin is used to determine
either 3.3V or 5V signaling on the secondary bus.
S_VIO must be tied to 3.3V only when all devices on
the secondary bus use 3.3V signaling. Otherwise, S_VIO
is tied to 5V.
Bus/Power Clock Control Management Pin: When
this pin is tied HIGH and the PI7C8150B is placed in the
D3
the secondary bus in the B2 power state. The secondary
clocks are disabled and driven to 0. When this pin is tied
LOW, there is no effect on the secondary bus clocks
when the PI7C8150B enters the D3
APRIL 2006 – Revision 2.02
HOT
power state, it enables the PI7C8150B to place
PI7C8150B
HOT
power state.