pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 83

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
14.1.29
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Bit
22
23
24
25
26
27
31-28
Bit
0
1
3:2
Function
Secondary
Interface Reset
Fast Back-to-
Back Enable
Primary Master
Timeout
Secondary
Master Timeout
Master Timeout
Status
Discard Timer
P_SERR_L
enable
Reserved
Function
Reserved
Memory Write
Disconnect
Control
Reserved
Type
R/W
R/W
R/W
R/W
R/WC
R/W
R/O
Type
R/O
R/W
R/O
Page 83 of 108
Description
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Reserved. Returns 0 when read. Reset to 0.
Description
Controls the assertion of S_RESET_L signal pin on the secondary
interface
0: does not force the assertion of S_RESET_L pin
1: forces the assertion of S_RESET_L
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
Set’s the maximum number of PCI clocks the bridge will wait for an
initiator on the primary to repeat a delayed transaction request. The
counter starts right after the delayed transaction is at the front of the
queue. If the master has not repeated at least once before the counter
expires, the bridge discards the transaction from the queue.
0: 2
1: 2
Reset to 0
Set’s the maximum number of PCI clocks the bridge will wait for an
initiator on the secondary to repeat a delayed transaction request. The
counter starts right after the delayed transaction is at the front of the
queue. If the master has not repeated at least once before the counter
expires, the bridge discards the transaction from the queue.
0: 2
1: 2
Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
This bit is set to 1 and P_SERR_L is asserted when either the
primary discard timer or the secondary discard timer expire.
Reset to 0
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
15
10
15
10
PCI clocks
PCI clocks
PCI clocks
PCI clocks
APRIL 2006 – Revision 2.02
PI7C8150B