pi7c8150b Pericom Semiconductor Corporation, pi7c8150b Datasheet - Page 50

• Manufacturer Part Number: pi7c8150b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0044
6.2
6.2.1
When PI7C8150B detects an address parity error on the secondary interface, the following
events occur:
DATA PARITY ERRORS
When forwarding transactions, PI7C8150B attempts to pass the data parity condition from
one interface to the other unchanged, whenever possible, to allow the master and target
devices to handle the error condition.
The following sections describe, for each type of transaction, the sequence of events that
occurs when a parity error is detected and the way in which the parity condition is
forwarded across PI7C8150B.
CONFIGURATION WRITE TRANSACTIONS TO
CONFIGURATION SPACE
When PI7C8150B detects a data parity error during a Type 0 configuration write
transaction to PI7C8150B configuration space, the following events occur:
If the parity error response bit is set in the command register, PI7C8150B asserts
P_TRDY_L and writes the data to the configuration register. PI7C8150B also asserts
P_PERR_L. If the parity error response bit is not set, PI7C8150B does not assert
P_PERR_L.
If the parity error response bit is set in the command register, PI7C8150B does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts the transaction if it is directed to or across PI7C8150B.
PI7C8150B sets the detected parity error bit in the status register.
PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
If the parity error response bit is set in the bridge control register, PI7C8150B does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts transaction if it is directed to or across PI7C8150B.
PI7C8150B sets the detected parity error bit in the secondary status register.
PI7C8150B asserts P_SERR_L and sets signaled system error bit in status register, if
both of the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the command register.
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register.
Page 50 of 108
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
APRIL 2006 – Revision 2.02
PI7C8150B