pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 118

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Command Phase
Execution Phase
5.7.6
The LOCK command can be used to keep the FIFO en-
abled and to retain the values of some parameters after a
software reset.
After the command byte of the LOCK command is written,
its result byte must be read before the opcode of the next
command can be read. The LOCK command is not execut-
ed until its result byte is read by the microprocessor.
If the part is reset after the command byte of the LOCK com-
mand is written but before its result byte is read, then the
LOCK command is not executed. This prevents accidental
execution of the LOCK command.
Perpendicular
7
None.
Toshiba
Format
Format
Format
(MFM)
(MFM)
IBM
ISO
FIGURE 5-19. IBM, Perpendicular, and ISO Formats Supported by the FORMAT TRACK Command
The LOCK Command
6
5
Index Pulse
Gap 0
Gap 0
A1* = Data Pattern of A1, Clock Pattern of 0A. All other data rates use gap 2 = 22 bytes.
C2* = Data Pattern of C2, Clock Pattern of 14
80 of
80 of
4E
4E
Invalid Opcodes
SYNC
SYNC
12 of
12 of
4
00
00
Address
Index
Field
3 of
C2* FC
3 of
C2* FC
IAM
IAM
3
Gap 1
Gap 1
Gap 1
50 of
50 of
32 of
4E
4E
4E
2
SYNC
SYNC
SYNC
12 of
12 of
12 of
00
00
00
1
3 of
A1* FE
3 of
A1* FE
3 of
A1* FE
AM
AM
AM
Address Field
0
T
r
a
c
k
T
r
a
c
k
T
r
a
c
k
118
H
e
a
d
H
e
a
d
H
e
a
d
Result Phase
The system reads the value 80h from ST0 indicating that an
invalid command was received.
Command Phase
Bit 7 - Control Reset Effect (LOCK)
Execution Phase
S
e
c
t
o
r
S
e
c
t
o
r
S
e
c
t
o
r
LOCK
Repeated for each sector
7
7
#
B
y
t
e
s
#
B
y
t
e
s
#
B
y
t
e
s
This bit determines how the FIFO, THRESH, and
PRETRK bits in the CONFIGURE command and, the
FWR, FRD, and BST bits in the MODE command are af-
fected by a software reset.
0: Set default values after a software reset. (Default)
1: Values are unaffected by a software reset.
Internal register is written.
C
R
C
C
R
C
C
R
C
Result Phase Status Register 0 (STO) (80h)
Gap 2
Gap 2
Gap 2
22 of
41 of
22 of
4E
4E
4E
6
6
0
SYNC
SYNC
SYNC
12 of
12 of
12 of
00
00
00
5
5
0
3 of
A1*
3 of
A1*
3 of
A1*
AM
AM
AM
FB
or
F8
FB
or
F8
FB
or
F8
4
4
1
Data Field
Data
Data
Data
3
3
0
2
2
1
C
R
C
C
R
C
C
R
C
Program-
Program-
Program-
Gap 3
Gap 3
Gap 3
able
able
able
1
1
0
Gap 4
Gap 4
Gap 4
0
0
0