pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 201

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 0 - FIFO Enable (FIFO_EN)
Bit 1 - Receiver Soft Reset (RXSR)
Bit 2 - Transmitter Soft Reset (TXSR)
Bit 3 - Reserved
Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
0
7
When set to 1 enables both the Transmision and Recep-
tion FIFOs. Resetting this bit clears both FIFOs.
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Read/Write 0.
In Non-Extended modes, these bits have no effect.
In Extended modes, these bits select the TX_FIFO in-
terrupt threshold level. An interrupt is generated when
the level of the data in the TX_FIFO drops below the en-
coded threshold.
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded thresh-
old.
RXFTH1
0
6
RXFTH0
TXFTH (Bits 5,4) TX_FIF0 Threshold
TABLE 8-4. TX_FIFO Level Selection
0
5
FIGURE 8-9. FCR Register Bitmap
00(Default)
TXFTH1
0
4
TXFTH0
01
10
11
0
0
3
Reserved
0
2
Write Cycles
TXSR
0
1
RXSR
0
0
Reset
Required
FIFO_EN
Enhanced Serial Port - UART1 (Logical Device 6)
13
1
3
9
Register (FCR)
FIFO Control
Offset 02h
Bank 0,
201
8.5.5
The Line Control Register (LCR) and the Bank Select
Register (BSR) (see the next register) share the same ad-
dress.
The Line Control Register (LCR) selects the communica-
tions format for data transfers.
Upon reset, all bits are set to 0.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Line Control Register (SH_LCR) register in
bank 3 (See Section 8.8.2 on page 210). During a write op-
eration to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
Upon reset, all bits are set to 0.
Line Control Register (LCR)
Bits 1,0 - Character Length Select (WLS1,0)
0
7
If bit 7 is 0, the write affects both LCR and BSR.
If bit 7 is 1, the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
These bits specify the number of data bits in each trans-
mitted or received serial character. Table 8-6 shows
how to encode these bits.
0
6
BKSE
Line Control Register (LCR) and Bank
Selection Register (BSR)
SBRK
RXFTH (Bits 5,4) RX_FIF0 Threshold
TABLE 8-5. RX_FIFO Level Selection
0
5
FIGURE 8-10. LCR Register Bitmap
00(Default)
0
4
STKP
EPS
01
10
11
0
3
PEN
0
2
STB
0
1
WLS1
0
0
Reset
Required
WLS0
14
1
4
8
Register (LCR)
Line Control
All Banks,
Offset 03h
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