pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 200

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

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Event Identification Register (EIR), Extended Mode
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
EIR Bits
0
3 2 1 0
0 0 0 1
0 1 1 0
0 1 0 0
1 1 0 0
0 0 0 0
FIGURE 8-8. EIR Register Bitmap, Extended Mode
7
0 0 1 0
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
Reserved
0
6
Reserved
0
5
TXEMP-EV
Extended Mode, Read Cycles
0
Priority
4
Highest
Second
Second
Fourth
Level
Third
Reserved
0
3
MS_EV
0
2
LS_EV or TXHLT_EV
0
1
RX_FIFO Time-
Transmitter Low
Interrupt Type
Modem Status Any transition on CTS, DSR or DCD or a
Receiver High
Line Status
TXLDL_EV
Data Level
Data Level
1
0
Event
Event
None
RXHDL_EV
Reset
Required
Out
TABLE 8-3. Non-Extended Mode Interrupt Priorities
Enhanced Serial Port - UART1 (Logical Device 6)
Event Identification
Parity error, framing error, data overrun
or break event
Receiver Holding Register (RXD) full, or
RX_FIFO level equal to or above
threshold.
At least one character is in the
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
Transmitter Holding Register or
TX_FIFO empty.
low to high transition on RI.
Register (EIR)
Offset 02h
Interrupt Set and Reset Functions
Bank 0,
Interrupt Source
200
None
Bit 2 - Line Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
Bit 3 - Modem Status Event (MS_EV)
Bit 4 - Reserved
Bit 5 - Transmitter Empty (TXEMP_EV)
Bits 7,6 - Reserved
8.5.4
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
This bit is set to 1 when a receiver error or break condi-
tion is reported.
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
Read/Write 0.
This bit is the same as bit 6 of the LSR register. It is set
to 1 when the transmitter is empty.
Read/Write 0.
FIFO Control Register (FCR)
Read Line Status Register (LSR).
Reading the RXD or, RX_FIFO level
drops below threshold.
Reading the RXD port.
Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
Reading the Modem Status Register
(MSR).
Interrupt Reset Control