pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 57

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Bit 7 - Update in Progress (UIP)
TABLE 4-3. Divider Chain Control and Bank Selection
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6
This read only bit is not affected by reset.
0: An update will not occur within the next 244 sec.
1: Timing registers are updated within 244 sec.
DV2-0
AF bit of CRC
PF bit of CRC
UIP bit of CRA
UF bit of CRC
1. The oscillator stops in this case only in the event
of a power failure.
5 4
Bit 7 (the SET bit) of Control Register B (CRB) is 1.
Undefined
Selected
Bank 0
Bank 0
Bank 0
Bank 1
Bank 2
Bank 0
Bank 0
A-B
D-C
C-E
UIP
UF
PF
AF
Flags (and IRQ) are reset at the conclusion of Control Register C (CRC) read or by reset.
Bank
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Update In Progress (UIP) bit high before update occurs = 244 sec
Periodic interrupt to update = Period (periodic int) / 2 + 244 sec
Update to Alarm Interrupt = 30.5 s
Update In Progress status bit
Update-Ended Interrupt Flag (Update-Ended Interrupt if enabled)
Periodic Flag (Periodic Interrupt if enabled)
Alarm Flag (Alarm Interrupt if enabled)
D
Divider Chain Reset
Divider Chain Reset
Oscillator Disabled
Oscillator Disabled
Normal Operation
Normal Operation
Normal Operation
Configuration
Test
FIGURE 4-5. Interrupt/Status Timing
1
1
A
57
4.2.2
This register enables the selection of various time and date
options, as well as the use of interrupts.
Bit 0 - Daylight Savings Enable (DSE)
Bit 1 - 24 or 12 Hour Mode
Bit 2 - Data Mode (DM)
7
Master reset does not affect this read/write bit.
0: Disables the daylight savings feature.
1: Enables daylight savings feature, as follows:
This is a read/write bit that is not affected by reset.
0: Enables 12 hour format.
1: Enables 24 hour format.
This is a read/write bit that is not affected by reset.
0: Enables BCD format.
1: Enables binary format.
SET
6
0
In the spring, time advances from 1:59:59 to
3:00:00 on the first Sunday in April.
In the fall, time returns from 1:59:59 to 1:00:00 on
the last Sunday in October.
RTC Control Register B (CRB)
PIE
5
0
FIGURE 4-4. CRB Register Bitmap
C
B
AIE
4
0
3
0
0
UIE
Unused
2
E
DM
1
24 or 12 Hour Mode
0
Power-Up
Reset
Required
DSE
RTC Control
Register B
Index 0Bh
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(CRB)