pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 63

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Conditions that put the ONCTL flip-flop in a 1 state (inactive
ONCTL signal):
Power Override
When the debounced SWITCH is 0 and Vdd exists (both)
for more than 3.95 seconds or 4 seconds (the time is select-
ed via bit 3 of the APCR7 register), ONCTL is deasserted
regardless of the Fail-safe Timer state. Once a power but-
ton override is detected, the ONCTL can be asserted again
only after Vdd does not exist.
For the last 500 msec ONCTL is asserted but Vdd does not
exist. This reset condition overrides any set condition of the
ONCTL flip-flop. This condition can reset the ONCTL flip-
flop, only if enabled via bit 4 of APCR7 register.
User software must ensure unused date/time fields are
coherent, to ensure the comparison of valid bits gives
the correct results.
The RING enable bit (bit 3 of APCR2) is 1 and one of
the following occurs:
— Bit 2 of APCR2 is 0, and a high-to-low transition is
— Bit 2 of APCR2 is 1 and a train of pulses is detected
RI1,2 Enable bits (bits 3 and 4 of APCR2) are 1 and a
high to low transition is detected on the RI1,2 input
pin(s).
Software On Command by asserting bit 7 of APCR2
PME1 Status bit (GP1_STS0 bit 0) and PME1 Enable
bit (GP1_EN0 bit 0) are set.
PME2 Status bit (GP1_STS0 bit 1) and PME2 Enable
bit (GP1_EN0 bit 1) are set.
IRRX1 Status bit (GP1_STS0 bit 2) and IRRX1 Enable
(GP1_EN0 bit 2) bit are set.
IRRX2 Status bit (GP1_STS0 bit 3) and IRRX2 Enable
(GP1_EN0 bit 3) bit are set.
GPIO10 Status bit (GP1_STS0 bit 6) and GPIO10 En-
able bit (GP1_EN0 bit 6) are set.
Switch Off Delay Enable bit is 0 and Switch Off event
occurred. (The Switch-Off event can inactivate ONCTL
only when SCI/POR bit is 0 - see PM1_CNT_LOW
register in the ACPI Fixed registers). The Power But-
ton Enable bit has no effect - see PM1_EN_HIGH reg-
ister in the ACPI Fixed registers.
Switch Off Delay Enable bit is 1 and Fail-safe Timer
reached terminal count. (The Failsafe Timer’s terminal
count can inactivate ONCTL only when SCI/POR bit is
0 - see PM1_CNT_LOW register in the ACPI Fixed
registers). The Power Button Enable bit has no effect -
see PM1_EN_HIGH register in the ACPI Fixed regis-
ters.
Software Off Command by asserting bit 5 of APCR1.
detected on the RING input pin.
on the RING input pin.
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
63
When Activate and Inactivate conditions of the ONCTL flip-
flop occur at the same time, the Activate overrides the Inac-
tivate. Exception to this are the following Inactivate condi-
tions. They override any Activate condition that occurs at
the same time:
When bit 4 of APCR7 register is 0, ONCTL can be asserted
only after 1 second passed since it was deasserted. A wake
up event that happens during this 1 second, will activate the
ONCTL signal at the end of the 1 second. Off events are ig-
nored during the 1 second period.
When bit 4 of APCR7 register is 1, ONCTL can be asserted
immediately after it was deasserted. (i.e., a wake-up event
can activate ONCTL immediately after ONCTL was deas-
serted.)
The t
Timing" on page 265) delay on power-up, when power re-
turns after power failure, always occurs, regardless of bit 4
of APCR7 register.
The SWITCH pin is 0 for more than 3.95 seconds or 4
seconds. See detailed description above.
For the last 500 msec ONCTL is asserted but Vdd
does not exist. See detailed description above.
ONH
(see TABLE 14-69 "RING Trigger and ONCTL
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