pc87317vul National Semiconductor Corporation, pc87317vul Datasheet - Page 163

• Manufacturer Part Number: pc87317vul
• Description: Pc87317vul/pc97317vul Superi/o Plug And Play Compatible With Acpi Compliant Controller/extender
• Manufacturer: National Semiconductor Corporation

Data transfer takes place by use of data buffers that inter-
face internally in parallel and with the external data channel
in a serial format. 16-byte data FIFOs may reduce host
overhead by enabling multiple-byte data transfers within a
single interrupt. With FIFOs disabled, this module is equiv-
alent to the standard 16450 UART. With FIFOs enabled, the
hardware functions as a standard 16550 UART.
The composite serial data stream interfaces with the data
channel through signal conditioning circuitry such as
TTL/RS232 converters, modem tone generators, etc.
Data transfer is accompanied by software-generated con-
trol signals, which may be utilized to activate the communi-
cations channel and “handshake” with the remote device.
These may be supplied directly by the UART, or generated
by control interface circuits such as telephone dialing and
answering circuits, etc.
The composite serial data stream produced by the UART is
illustrated in Figure 7-2. A data word containing five to eight
bits is preceded by start bits and followed by an optional
parity bit and a stop bit. The data is clocked out, LSB first,
at a predetermined rate (the baud).
The data word length, parity bit option, number of start bits
and baud are programmable parameters.
The UART includes a programmable Baud Generator that
produces the baud clocks and associated timing signals for
serial communication.
The system can monitor this module status at any time. Sta-
tus information includes the type and condition of the trans-
fer operation in process, as well as any error conditions
(e.g., parity, overrun, framing, or break interrupt).
The module resources include modem control capability
and a prioritized interrupt system. Interrupts can be pro-
grammed to match system requirements, minimizing the
CPU overhead required to handle the communications link.
Programmable Baud Generator
This module contains a programmable Baud Generator that
generates the clock rates for serial data communication
(both transmit and receive channels). It divides its input
clock by any divisor value from 1 to 2
frequency of the Baud Generator must be programmed to
be sixteen times the baud value. A 24 MHz input frequency
is divided by a prescale value (PRESL field of EXCR2 - see
page 180. Its default value is 13) and by a 16-bit program-
mable divisor value contained in the Baud Generator Divi-
sor High and Low registers (BGD(H) and BGD(L) - see page
178). Each divisor value yields a clock signal (BOUT) and a
further division by 16 produces the baud clock for the serial
data stream. It may also be output as a test signal when en-
abled (see bit 7 of EXCR1 on page 178.)
These user-selectable parameters enable the user to gen-
erate a large choice of serial data rates, including all stan-
dard baud rates. A list of baud rates and their settings
appears in Table 7-14 on page 178.
Module Operation
Before module operation can begin, both the communica-
tions format and baud must be programmed by the soft-
ware. The communications format is programmed by
START -LSB- DATA 5-8 -MSB- PARITY
FIGURE 7-2. Composite Serial Data
Enhanced Serial Port with IR - UART2 (Logical Device 5)
16
- 1. The output clock
STOP
163
loading a control byte into the LCR register, while the baud
is selected by loading an appropriate value into the Baud
Generator Divisor Registers and the divisor preselect val-
ues (PRESL) into EXCR2 (see page 180).
The software can read the status of the module at any time
during operation. The status information includes full or
empty state for both transmission and reception channels,
and any other condition detected on the received data
stream, like parity error, framing error, data overrun, or
break event.
7.4.2
In Extended UART mode of operation, the module configu-
ration changes and additional features become available
which enhance UART capabilities.
7.5 SHARP-IR MODE – DETAILED DESCRIPTION
This mode supports bidirectional data communication with
a remote device using infrared radiation as the transmission
medium. Sharp-IR uses Digital Amplitude Shift Keying
(DASK) and allows serial communication at baud rates up
to 38.4 Kbaud. The format of the serial data is similar to the
UART data format. Each data word is sent serially begin-
ning with a zero value start bit, followed by up to eight data
bits (LSB first), an optional parity bit, and ending with at
least one stop bit with a binary value of one. A logical zero
is signalled by sending a 500 KHz continuous pulse train of
infrared radiation. A logical 1 is signalled by the absence of
any infrared signal. This module can perform the modula-
tion and demodulation operations internally, or can rely on
the external optical module to perform them.
Sharp-IR device operation is similar to the operation in
UART mode, the main difference being that data transfer
operations are normally performed in half duplex fashion,
and the modem control and status signals are not used. Se-
lection of the Sharp-IR mode is controlled by the Mode Se-
lect (MDSL) bits in the MCR register when the module is in
Extended mode, or by the IR_SL bits in the IRCR1 register
when the module is not in extended mode. This prevents
legacy software, running in non-extended mode, from spu-
riously switching the module to UART mode, when the soft-
ware writes to the MCR register.
7.6 SIR MODE – DETAILED DESCRIPTION
This operational mode supports bidirectional data commu-
nication with a remote device using infrared radiation as the
transmission medium.
SIR allows serial communication at baud rates up to
115.2 Kbuad. The serial data format is similar to the UART
data format. Each data word is sent serially beginning with
The interrupt sources are no longer prioritized; they
are presented bit-by-bit in the EIR (see page 168).
An auxiliary status and control register replaces the
scratchpad register. It contains additional status and
control flag bits (“Auxiliary Status and Control Register
(ASCR)” on page 176).
The TX_FIFO can generate interrupts when the num-
ber of outgoing bytes in the TX_FIFO drops below a
programmable threshold. In the Non-Extended UART
modes, only reception FIFOs have the thresholding
feature.
DMA capability is available.
Interrupts occur when the transmitter becomes empty
or a DMA event occurs.
Extended UART Mode
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