mpc970 Freescale Semiconductor, Inc, mpc970 Datasheet - Page 13

• Manufacturer Part Number: mpc970
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Freescale Semiconductor, Inc

should an error occur in the loading of the Serial Input
Register. The user may programmably freeze an output clock
by writing logic ‘0’ to the respective freeze enable bit.
Likewise, the user may programmably unfreeze an output
clock by writing logic ‘1’ to the respective enable bit.
frozen simultaneously by placing a logic ‘0’ on the Com_Frz
input and then issuing a low going pulse on the Frz_Strobe
input. Likewise, all 15 clocks can be simultaneously unfrozen
by placing logic ‘1’ on the Com_Frz input and then issuing a
low–going pulse on the Frz_Strobe input. Note that all 15
clocks are affected by the Frz_Strobe freeze logic.
logic ‘0’ state before the time at which it would normally
transition there. The logic simply keeps the frozen clock at
logic ‘0’ once it is there. Likewise, the freeze logic will never
force a newly–unfrozen clock to a logic ‘1’ state before the
time at which it would normally transition there. The logic
re–enables the unfrozen clock during the time when the
respective clock would normally be in a logic ‘0’ state,
eliminating the possibility of ‘runt’ clock pulses.
Frz_Data input by supplying a logic ‘0’ start bit followed
serially by 13 NRZ freeze enable bits. After the 13th freeze
enable bit the Frz_Data signal must be left in (or returned to)
a logic ‘1’ state (Figure 12). The period of each Frz_Data bit
equals the period of the free–running Frz_Clk signal. The
Frz_Data serial transmission should be timed so the
MPC970 can sample each Frz_Data bit with the rising edge
of the free–running Frz_Clk signal.
simplify system level implementation. The serial input port
can be used to establish the freeze mask to disable the
appropriate outputs. The Frz_Strobe input can then be used
to unfreeze the outputs without having to serially load an “all
unfrozen” freeze mask.
TIMING SOLUTIONS
BR1333 — Rev 6
The second freeze mechanism allows all 15 clocks to be
The freeze logic will never force a newly–frozen clock to a
The user may write to the Serial Input register through the
The user can combine the two freeze capabilities to
Start
Bit
D0
D0 is the control bit for 2x_PCLK
D1 is the control bit for PCLKEN
D2 is the control bit for BCLKEN
D3–D6 are the control bits for BCLK1–BCLK4
D7–D12 are the control bits for PCI_CLK1–PCI_CLK6
Figure 12. Freeze Data Input Protocol
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11
D12
13
Driving the PowerPC 601 Microprocessor
the MPC970 clock driver. A 2x_PCLK input at twice the
internal MPC 601 clock rate and the PCLKEN and BCLKEN
signals used to mask internal clock edges. The PCLKEN
signal always runs at one half the 2x_PCLK signal while the
BCLKEN signal can run at 1x, 1/2x, 1/3x or 1/4x the PCLK
input signal depending on the speed of the processor bus.
When the BCLKEN signal is running at 1/3 or 1/4 the PCLK
input the input duty cycle must be 66/33 and 75/25
respectively. In addition, as shown in Figure 13, to satisfy the
BCLKEN to 2x_PCLK Hold specification the BCLKEN signal
must be at least coincident with the 2x_PCLK edge. To
simplify board level implementation it would be desirable that
the BCLKEN signal actually lag the 2x_PCLK by a few
hundred picoseconds. The MPC970 insures that its BCLKEN
output always lags the 2x_PCLK input by at least 300ps.
frequencies which can be realized using the MPC970 clock
driver.
Table 4. Common MPC601 System Frequencies
2x_PCLK
PCLKEN
BCLKEN
The MPC601 processor requires three clock inputs from
Table 4 illustrates some typical MPC 601 system
2x_PCLK
240
240
240
200
200
200
160
160
132
132
Figure 13. MPC601 Setup and Hold Times
t s
t h
PCLK
120
120
120
100
100
100
80
80
66
66
60(1/2x)
40(1/3x)
30(1/4x)
50(1/2x)
33(1/3x)
25(1/4x)
40(1/2x)
20(1/4x)
33(1/2x)
BCLK
66(1x)
t s
t h
MPC970
PCI_CLK
MOTOROLA
30(1/2x)
20(1/2x)
25(1/2x)
20(1/2x)
33(1/2x)
30(1x)
33(1x)
25(1x)
20(1x)
33(1x)