mpc970 Freescale Semiconductor, Inc, mpc970 Datasheet - Page 8

• Manufacturer Part Number: mpc970
• Description: Low Voltage Pll Clock Driver
• Manufacturer: Freescale Semiconductor, Inc

MPC970
MR/Tristate
internal flip flops and also tristate all of the clock outputs. This
input is used primarily for IC and board level test.
Ref_Sel
sources for the PLL reference frequency. For the MPC970,
LOW on Ref_Sel will choose the LVCMOS TCLK input. For
the MPC970, a HIGH on Ref_Sel will choose the crystal
oscillator input.
2x_PCLK
implementation in a PowerPC 601 microprocessor based
system. In the MPC601_Clk mode the 2x_PCLK will run at
half the internal VCO frequency. With a maximum internal
VCO frequency of 1000MHz this output could theoretically
toggle at 500MHz, in practice however the output can toggle
only as fast as 300MHz. This frequency will be required on
future enhancements to the MPC 601 microprocessor. When
the MPC970 is taken out of the MPC601_Clk mode the
2xPCLK will run at a VCO/4 frequency. This divide ratio will
place this output frequency in the present and future
processor bus speeds of the PowerPC 603, PowerPC 604
and Pentium microprocessors. The 2x_PCLK output is a
50% duty cycle LVCMOS output.
PCLKEN
input of the PowerPC 601 microprocessor when the MPC970
is in the MPC601_Clk mode. The PCLKEN output frequency
is one half that of the 2x_PCLK output, a divide by four of the
internal VCO. The PCLKEN output runs at the same
frequency regardless of the state of the frequency divide
controls. The toggle frequency of this output is well placed for
driving the PowerPC 603, PowerPC 604 and Pentium
processor buses. The PCLKEN output is a 50% duty cycle
LVCMOS output.
Programming the MPC970
frequency relationships of the various outputs as well as the
relationships between the input references and outputs. The
purpose of this section is to outline the various relationships.
Although not exhaustive the hope is that enough information
is supplied to allow the customers to tailor the I/O
relationships for their specific applications.
oscillator. The VCO exhibits a very wide frequency range to
allow for a great deal of flexibility to the end user. Special
design techniques were used in the overall PLL design to
MOTOROLA
The MR/Tristate input when pulled LOW will reset all of the
The Ref_Sel input allows the user to choose between two
In general the outputs are named based on the
The PCLKEN output is designed to drive the PCLKEN
The MPC970 is very flexible in the programming of the
The VCO used in the MPC970 is a differential ring
APPLICATIONS INFORMATION
8
BCLKEN
input of the PowerPC 601 microprocessor when the MPC970
is in the MPC601_Clks mode. The BCLKEN toggles at the
same frequency as the BCLK outputs as described earlier.
However when the BCLKEN output is a divide by three or a
divide by four of the PCLKEN output the duty cycle is 66/33
and 75/25 respectively per the requirement of the MPC 601
processor. In addition to meet the HOLD time spec for the
BCLKEN input of the MPC 601 the BCLKEN output of the
MPC970 lags the 2xPCLK output by no less than 100ps.
When the MPC970 is not in the MPC601_Clks mode the
BCLKEN output is set at a fixed divide by four from the
internal VCO. In addition in this mode the BCLKEN output
does NOT lag the other outputs, but rather is synchronous
within the Output–to–Output skew spec of the device.
BCLK0:4
the processor bus of either the PowerPC or Pentium
microprocessors. The most common practice in “non MPC
601” applications will be to place these outputs in the
PCLKEN/1 mode and combine them with the above outputs
to drive all of the loads on the processor bus. The division
ratios do allow for the swap of these outputs with the
PCI_CLK outputs if more clocks are needed to drive the
processor bus. For PowerPC 601 microprocessor based
systems the division ratios allow the processor internal
speeds to be increased while maintaining reasonable speeds
for the L2 cache and the PCI bridge chip. The BCLK outputs
are 50% duty cycle LVCMOS outputs.
PCI_Clk0:6
designed to drive the PCI bus clock loads in a typical
microprocessor based system. The division ratios allow for
these outputs to remain in the
various common processor bus speeds as well as higher
future processor bus speeds. These outputs can also be
programmed to run at the processor bus speeds if more
processor bus clocks are required. The PCI_CLK outputs are
50% duty cycle LVCMOS outputs.
keep the relatively high gain of the VCO from significantly
impacting the jitter of the PLL.
different modes defined by the division select input pins. In
this table the VCO_Sel pin is high so that the 2 prescaler is
bypassed. Note that the 32 feedback is always fed directly
from the VCO and is thus unaffected by the level on the
VCO_Sel input. Table 1 shows each of the output
frequencies as a function of the VCO frequency. The two
VCO ranges can be used to plug in values to get the actual
frequencies. When the internal feedback option is used the
multiplication factor of the device will equal 32 divided by the
The BCLKEN output is designed to drive the BCLKEN
The BCLK outputs are designed to drive the clock loads on
As the name would suggest the PCI_CLK outputs are
Table 1 tabulates the various output frequencies for the
33MHz PCI bus speeds for
TIMING SOLUTIONS
BR1333 — Rev 6