mm74hc245a Fairchild Semiconductor, mm74hc245a Datasheet

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mm74hc245a

Manufacturer Part Number
mm74hc245a
Description
Mm74hc245a Octal 3-state Transceiver
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2005 Fairchild Semiconductor Corporation
MM74HC245AWM
MM74HC245ASJ
MM74HC245AMTC
MM74HC245AN
MM74HC245A
Octal 3-STATE Transceiver
General Description
The MM74HC245A 3-STATE bidirectional buffer utilizes
advanced silicon-gate CMOS technology, and is intended
for two-way asynchronous communication between data
buses. It has high drive current outputs which enable high
speed operation even when driving large bus capaci-
tances. This circuit possesses the low power consumption
and high noise immunity usually associated with CMOS cir-
cuitry, yet has speeds comparable to low power Schottky
TTL circuits.
This device has an active LOW enable input G and a direc-
tion control input, DIR. When DIR is HIGH, data flows from
the A inputs to the B outputs. When DIR is LOW, data flows
from the B inputs to the A outputs. The MM74HC245A
transfers true data from one bus to the other.
This device can drive up to 15 LS-TTL Loads, and does not
have Schmitt trigger inputs. All inputs are protected from
damage due to static discharge by diodes to V
ground.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignments for DIP, SOIC, SOP and TSSOP
Package Number
Top View
MTC20
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005165
CC
and
Features
Truth Table
H
L
X
Typical propagation delay: 13 ns
Wide power supply range: 2–6V
Low quiescent current: 80
3-STATE outputs for connection to bus oriented systems
High output drive: 6 mA (minimum)
Same as the 645
LOW Level
Irrelevant
HIGH Level
Package Description
G
H
L
L
Control
Inputs
DIR
H
L
X
P
A maximum (74 HC)
September 1983
Revised May 2005
B data to A bus
A data to B bus
Operation
Isolation
www.fairchildsemi.com

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mm74hc245a Summary of contents

Page 1

... DIR. When DIR is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from the B inputs to the A outputs. The MM74HC245A transfers true data from one bus to the other. This device can drive LS-TTL Loads, and does not have Schmitt trigger inputs ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage DIR and G pins ( Input/Output Voltage ( OUT Clamp Diode Current ( Output Current, ...

Page 4

AC Electrical Characteristics q 5V 6ns Symbol Parameter Maximum Propagation Delay PHL PLH Maximum Output Enable PZH PZL Time Maximum Output ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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