mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 135

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

9.4 Latching of Interrupts
MC68HC912DG128 — Rev 3.0
MOTOROLA
Vector Address
$FFDC, $FFDD
$FFEC, $FFED
$FFDE, $FFDF
$FFFC, $FFFD
$FFEE, $FFEF
$FFEA, $FFEB
$FFFE, $FFFF
$FFFA, $FFFB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
Reset
Clock monitor fail reset
COP failure reset
Unimplemented instruction trap
SWI
XIRQ
IRQ
Real time interrupt
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Pulse accumulator overflow
XIRQ is always level triggered and IRQ can be selected as a level
triggered interrupt. These level triggered interrupt pins should only be
released during the appropriate interrupt service routine. Generally the
interrupt service routine will handshake with the interrupting logic to
release the pin. In this way, the MCU will never start the interrupt service
sequence only to determine that there is no longer an interrupt source.
In the event that this does occur the trap vector will be taken.
If IRQ is selected as an edge triggered interrupt, the hold time of the level
after the active edge is independent of when the interrupt is serviced. As
long as the minimum hold time is met, the interrupt will be latched inside
the MCU. In this case the IRQ edge interrupt latch is cleared
automatically when the interrupt is serviced.
All of the remaining interrupts are latched by the MCU with a flag bit.
These interrupt flags should be cleared during an interrupt service
routine or when interrupts are masked by the I bit. By doing this, the
MCU will never get an unknown interrupt source and take the trap vector.
Interrupt Source
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 9-1. Interrupt Vector Map
Go to: www.freescale.com
Resets and Interrupts
Mask
None
None
None
None
None
CCR
X bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
COPCTL (CME, FCME)
COP rate selected
INTCR (IRQEN)
PACTL (PAOVI)
RTICTL (RTIE)
Local Enable
TMSK1 (C0I)
TMSK1 (C1I)
TMSK1 (C2I)
TMSK1 (C3I)
TMSK1 (C4I)
TMSK1 (C5I)
TMSK1 (C6I)
TMSK1 (C7I)
TMSK2 (TOI)
None
None
None
None
Resets and Interrupts
Latching of Interrupts
HPRIO Value to
Technical Data
Elevate
$EC
$DE
$DC
$EE
$EA
$F2
$F0
$E8
$E6
$E4
$E2
$E0
–
–
–
–
–
–
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