mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 36

• Manufacturer Part Number: mc68hc05ct4fn
• Description: Mc68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Interrupts
4.3 CPU Interrupt Processing
General Release Specification
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete.
If interrupts are not masked (I bit in the CCR is clear) and the
corresponding interrupt enable bit is set, the processor will proceed with
interrupt processing. Otherwise, the next instruction is fetched and
executed. If an interrupt occurs, the processor completes the current
instruction, stacks the current CPU register states, sets the I bit to inhibit
further interrupts, and finally checks the pending hardware interrupts. If
more than one interrupt is pending after the stacking operation, the
interrupt with the highest vector location shown in
serviced first. The SWI is executed the same as any other instruction,
regardless of the I-bit state.
When an interrupt is to be processed, the CPU fetches the address of
the appropriate interrupt software service routine from the vector table at
locations $1FF4–$1FFF as defined in
* External interrupts include IRQ and PORTC sources.
Register
CMCSR
CTCSR
SSSR
Freescale Semiconductor, Inc.
TSR
N/A
N/A
For More Information On This Product,
Table 4-1. Vector Address for Interrupts and Reset
OCF, ICF, TOF
TOFE, RTIE
Go to: www.freescale.com
CMP3
Name
SSIF
Flag
N/A
N/A
Interrupts
Reset
Software
CMP3, External Interrupts*
16-bit Timer Interrupts
SSI Interrupt
Core Timer Interrupts
Interrupt
Table
4-1.
TIMER, RTI
CMP3/IRQ
Interrupt
RESET
TIMER
MC68HC05CT4
CPU
SWI
SSI
Table 4-1
$1FFC–$1FFD
$1FFE–$1FFF
$1FFA–$1FFB
$1FF8–$1FF9
$1FF6–$1FF7
$1FF4–$1FF5
Address
will be
Vector
—
Rev. 2.0