mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 73

• Manufacturer Part Number: mc68hc05ct4fn
• Description: Mc68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

MC68HC05CT4
—
Rev. 2.0
Address:
being enabled. Always disable the SSI first, by clearing the SE bit, before
altering these control bits within the SSI control register (SCR).
SIE — SSI Interrupt Enable
SE — SSI Enable
LSBF — Least Significant Bit (LSB)First
MSTR — Master Mode
Reset:
Read:
Write:
This bit determines whether an interrupt request should be generated
when a transfer is complete.
When set, an interrupt request is made if the CPU is in the run or wait
mode of operation and status flag bit SF is set.
When cleared, no interrupt requests are made by the SSI.
When set, this bit enables the SSI, makes PD5 the SCK pin, and
makes PD4 the SDIO pin.
When SE is cleared, any transmission in progress is aborted, the bit
counter is reset, and pins SCK and SDIO revert to being PD5 and
PD4.
When set, data is sent and received in a least significant bit (LSB) first
format.
When cleared, data is sent and received in a most significant bit
(MSB) first format.
When set, this bit configures the SSI to the master mode. This means
that the transmission is initiated by a write to the data register and the
SCK pin becomes an output providing a synchronous data clock at a
rate determined by the SR bits.
Freescale Semiconductor, Inc.
For More Information On This Product,
$001E
Bit 7
SIE
Synchronous Serial Interface (SSI)
0
Go to: www.freescale.com
Figure 9-3. SSI Control Register (SCR)
SE
6
0
LSBF
5
0
MSTR
4
0
CPOL
Synchronous Serial Interface (SSI)
3
1
General Release Specification
T/R
2
0
SR1
1
0
SSI Registers
Bit 0
SR0
0