mc68hc05ct4fn Freescale Semiconductor, Inc, mc68hc05ct4fn Datasheet - Page 40

• Manufacturer Part Number: mc68hc05ct4fn
• Description: Mc68hc05 Family Of Microcontrollers Mcus
• Manufacturer: Freescale Semiconductor, Inc

Interrupts
4.8 External Interrupt Timing
4.9 16-Bit Timer Interrupt
4.10 SSI Interrupt
General Release Specification
When edge and level sensitivity is selected for the IRQ interrupt, it is
sensitive to the following cases:
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
the IRQ source. The interrupt request is then synchronized internally and
serviced as specified by the contents of $1FFA and $1FFB.
Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-
only trigger is available via the mask programmable option for
the IRQ pin.
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
Two different synchronous serial interrupt (SSI) flags cause an SSI
interrupt whenever they are set and enabled. The interrupt flags are in
the SSI status register (SSSR), and the enable bits are in the SSI control
register (SSCR). Either of these interrupts vector to the same interrupt
service routine, located at the address specified by the contents of
memory locations $1FF6 and $1FF7.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Low level on the IRQ pin
Falling edge on the IRQ pin
Falling edge or low level on any port C pin with keyscan enabled
Go to: www.freescale.com
Interrupts
MC68HC05CT4
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Rev. 2.0