mc68hc705k1 Freescale Semiconductor, Inc, mc68hc705k1 Datasheet - Page 41

• Manufacturer Part Number: mc68hc705k1
• Description: Hcmos Microcontroller Unit
• Manufacturer: Freescale Semiconductor, Inc

4.3.2.1 IRQ/V
MC68HC705K1 — Rev. 2.0
PP
Pin
An interrupt signal on the IRQ/V
request. After completing the current instruction, the CPU tests these
bits:
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
external interrupts.
The IRQ/V
low-level-triggered, depending on the state of the LEVEL bit in the mask
option register (MOR). See
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
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IRQ latch
IRQE bit in the interrupt status and control register
I bit in the condition code register
A falling edge or a low level on the IRQ/V
interrupt request.
As long as the IRQ/V
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/V
sources.
PP
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pin is negative edge-triggered only or negative edge- and
Interrupts
PP
9.6 Mask Option
PP
is low, an external interrupt request is
PP
pin of multiple wired-OR interrupt
pin latches an external interrupt
Figure 4-1
Register.
PP
shows the logic for
pin latches an external
Interrupt Types
Technical Data
Interrupts