mc68hc705k1 Freescale Semiconductor, Inc, mc68hc705k1 Datasheet - Page 54

• Manufacturer Part Number: mc68hc705k1
• Description: Hcmos Microcontroller Unit
• Manufacturer: Freescale Semiconductor, Inc

Resets
5.3.3 Computer Operating Properly (COP) Reset
5.3.4 Illegal Address Reset
Technical Data
Address:
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. (See
Watchdog.) To clear the COP watchdog and prevent a COP reset, write
a logic 0 to bit 0 (COPC) of the COP register at location $03F0. The COP
register is a write-only register that returns the contents of a ROM
location when read.
COPC — COP Clear Bit
An opcode fetch from an address that is not in the erasable,
programmable read-only memory (EPROM) (locations $0200–$03FF)
or the random-access memory (RAM) (locations $00E0–$00FF)
generates an illegal address reset. An illegal address reset pulls the
RESET pin low for one cycle of the internal clock.
Reset:
Read:
Write:
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Writing a logic 1
has no effect. Reset clears the COPC bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
$03F0
Bit 7
U
Go to: www.freescale.com
= Unimplemented
Figure 5-2. COP Register (COPR)
U
6
Resets
U
5
U = Unaffected
U
4
U
3
MC68HC705K1 — Rev. 2.0
U
2
8.5 COP
U
1
COPC
Bit 0
0